SI533价格

参考价格:¥720.5744

型号:SI53301/4-EVB 品牌:Fairchild 备注:这里有SI533多少钱,2025年最近7天走势,今日出价,今日竞价,SI533批发/采购报价,SI533行情走势销售排行榜,SI533报价。
型号 功能描述 生产厂家 企业 LOGO 操作
SI533

DUAL FREQUENCY CRYSTAL OSCILLATOR (XO) (10 MHZ TO 1.4 GHZ)

Description of Change: Silicon Labs is pleased to announce rev 1.2 for the Si530, Si531, Si532, Si533, Si534 devices. Please refer to Appendix A for a list of document changes and access to these datasheets online.

SILABS

芯科科技

SI533

DUAL-FREQUENCY CRYSTAL OSCILLATOR (XO) (10 MHZ TO 1.4 GHZ)

Features  Available with any-frequency output frequencies from 10 MHz to 945 MHz and select frequencies to 1.4 GHz  2 selectable output frequencies  3rd generation DSPLL® with superior jitter performance  3x better frequency stability than SAW-based oscillators  Pin 1 output enable (

SKYWORKS

思佳讯

Si533

Dual Low Jitter (XO)

SKYWORKS

思佳讯

Si533

Silicon Labs is pleased to announce rev 1.2 for the Si530

文件:170.98 Kbytes Page:2 Pages

SILABS

芯科科技

Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features  Supports single-ended or differential input clock signals  Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs  Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif

SKYWORKS

思佳讯

Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz

KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank option • 2:1

SKYWORKS

思佳讯

DUAL 1:5 LOW-JITTER, ANY-FORMAT BUFFER/ LEVEL TRANSLATOR ( GHZ)

Features  2 independent banks of 5x differential outputs  Ultra-low additive jitter: 45 fs rms  Wide frequency range: dc to 1.25 GHz  Any-format input with pin selectable output formats: LVPECL, Low Power LVPECL, LVDS, CML, HCSL, LVCMOS  Asynchronous output enable  Low output-outp

SKYWORKS

思佳讯

1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE ( GHZ)

Features  6 differential or 12 LVCMOS outputs  Ultra-low additive jitter: 45 fs rms  Wide frequency range: dc to 1.25 GHz  Universal input with pin selectable output formats  LVPECL, Low Power LVPECL, LVDS, CML, HCSL, LVCMOS  2:1 mux with hot-swappable inputs  Individual output en

SKYWORKS

思佳讯

Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz

KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank option • 2:1

SKYWORKS

思佳讯

Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz

KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank option • 2:1

SKYWORKS

思佳讯

DUAL 1:5 LOW-JITTER, ANY-FORMAT BUFFER/ LEVEL TRANSLATOR ( GHZ)

Features  2 independent banks of 5x differential outputs  Ultra-low additive jitter: 45 fs rms  Wide frequency range: dc to 1.25 GHz  Any-format input with pin selectable output formats: LVPECL, Low Power LVPECL, LVDS, CML, HCSL, LVCMOS  Asynchronous output enable  Low output-outp

SKYWORKS

思佳讯

1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE ( GHZ)

Features  6 differential or 12 LVCMOS outputs  Ultra-low additive jitter: 45 fs rms  Wide frequency range: dc to 1.25 GHz  Universal input with pin selectable output formats  LVPECL, Low Power LVPECL, LVDS, CML, HCSL, LVCMOS  2:1 mux with hot-swappable inputs  Individual output en

SKYWORKS

思佳讯

Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz

KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank option • 2:1

SKYWORKS

思佳讯

Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz

KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank option • 2:1

SKYWORKS

思佳讯

Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz

KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank option • 2:1

SKYWORKS

思佳讯

Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz

KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank option • 2:1

SKYWORKS

思佳讯

Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz

KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank option • 2:1

SKYWORKS

思佳讯

Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz

KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank option • 2:1

SKYWORKS

思佳讯

Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz

KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank option • 2:1

SKYWORKS

思佳讯

Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz

KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank option • 2:1

SKYWORKS

思佳讯

Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz

KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank option • 2:1

SKYWORKS

思佳讯

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features  Supports single-ended or differential input clock signals  Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs  Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif

SKYWORKS

思佳讯

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features  Supports single-ended or differential input clock signals  Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs  Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif

SKYWORKS

思佳讯

Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features  Supports single-ended or differential input clock signals  Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs  Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif

SKYWORKS

思佳讯

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features  Supports single-ended or differential input clock signals  Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs  Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif

SKYWORKS

思佳讯

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features  Supports single-ended or differential input clock signals  Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs  Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif

SKYWORKS

思佳讯

Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features  Supports single-ended or differential input clock signals  Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs  Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif

SKYWORKS

思佳讯

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features  Supports single-ended or differential input clock signals  Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs  Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif

SKYWORKS

思佳讯

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features  Supports single-ended or differential input clock signals  Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs  Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif

SKYWORKS

思佳讯

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features  Supports single-ended or differential input clock signals  Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs  Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif

SKYWORKS

思佳讯

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features  Supports single-ended or differential input clock signals  Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs  Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif

SKYWORKS

思佳讯

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features  Supports single-ended or differential input clock signals  Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs  Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif

SKYWORKS

思佳讯

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR

Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t

SILABS

芯科科技

SI533产品属性

  • 类型

    描述

  • 型号

    SI533

  • 制造商

    SILABS

  • 制造商全称

    SILABS

  • 功能描述

    DUAL FREQUENCY CRYSTAL OSCILLATOR(XO)(10 MHZ TO 1.4 GHZ)

更新时间:2025-12-29 14:20:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
SILICON
20+
SMD
3780
只做原装正品假一赔十!正规渠道订货!
SKYWORKS/思佳讯
25+
QFN-32
32000
SKYWORKS/思佳讯全新特价SI53301-B-GMR即刻询购立享优惠#长期有货
SILICON
21+
QFN-32
10
一级代理,专注军工、汽车、医疗、工业、新能源、电力
SILICON/芯科
24+
QFN
10000
只做原装
SILICON LABS
24+
con
10000
查现货到京北通宇商城
SILICON LABS/芯科
25+
QFN32
18000
全新原装现货,假一赔十
SILICON LABORATORIES INC
25+
2
公司优势库存 热卖中!
SILICON
23+
QFN
2556
原厂原装正品
A
2025+
5000
原装进口,免费送样品!
SILICON LABS(芯科)
2526+
QFN-32(5x5)
50000
只做原装优势现货库存,渠道可追溯

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