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SI5330价格
参考价格:¥720.5744
型号:SI53301/4-EVB 品牌:Fairchild 备注:这里有SI5330多少钱,2025年最近7天走势,今日出价,今日竞价,SI5330批发/采购报价,SI5330行情走势销售排行榜,SI5330报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
SI5330 | Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | ||
SI5330 | 1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features Supports single-ended or differential input clock signals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif | SKYWORKS 思佳讯 | ||
Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank option • 2:1 | SKYWORKS 思佳讯 | |||
DUAL 1:5 LOW-JITTER, ANY-FORMAT BUFFER/ LEVEL TRANSLATOR ( GHZ) Features 2 independent banks of 5x differential outputs Ultra-low additive jitter: 45 fs rms Wide frequency range: dc to 1.25 GHz Any-format input with pin selectable output formats: LVPECL, Low Power LVPECL, LVDS, CML, HCSL, LVCMOS Asynchronous output enable Low output-outp | SKYWORKS 思佳讯 | |||
1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE ( GHZ) Features 6 differential or 12 LVCMOS outputs Ultra-low additive jitter: 45 fs rms Wide frequency range: dc to 1.25 GHz Universal input with pin selectable output formats LVPECL, Low Power LVPECL, LVDS, CML, HCSL, LVCMOS 2:1 mux with hot-swappable inputs Individual output en | SKYWORKS 思佳讯 | |||
Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank option • 2:1 | SKYWORKS 思佳讯 | |||
Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank option • 2:1 | SKYWORKS 思佳讯 | |||
DUAL 1:5 LOW-JITTER, ANY-FORMAT BUFFER/ LEVEL TRANSLATOR ( GHZ) Features 2 independent banks of 5x differential outputs Ultra-low additive jitter: 45 fs rms Wide frequency range: dc to 1.25 GHz Any-format input with pin selectable output formats: LVPECL, Low Power LVPECL, LVDS, CML, HCSL, LVCMOS Asynchronous output enable Low output-outp | SKYWORKS 思佳讯 | |||
1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE ( GHZ) Features 6 differential or 12 LVCMOS outputs Ultra-low additive jitter: 45 fs rms Wide frequency range: dc to 1.25 GHz Universal input with pin selectable output formats LVPECL, Low Power LVPECL, LVDS, CML, HCSL, LVCMOS 2:1 mux with hot-swappable inputs Individual output en | SKYWORKS 思佳讯 | |||
Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank option • 2:1 | SKYWORKS 思佳讯 | |||
Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank option • 2:1 | SKYWORKS 思佳讯 | |||
Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank option • 2:1 | SKYWORKS 思佳讯 | |||
Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank option • 2:1 | SKYWORKS 思佳讯 | |||
Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank option • 2:1 | SKYWORKS 思佳讯 | |||
Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank option • 2:1 | SKYWORKS 思佳讯 | |||
Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank option • 2:1 | SKYWORKS 思佳讯 | |||
Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank option • 2:1 | SKYWORKS 思佳讯 | |||
Ultra-Low Additive Jitter Fanout Clock Buffers with up to 10 Universal Outputs from Any-Format Input and Wide Frequency Range from 1 MHz to 725 MHz KEY FEATURES • Ultra-low additive jitter: 50 fs rms • Built-in LDOs for high PSRR performance • Up to 10 outputs • Any-format Inputs (LVPECL, Low-power LVPECL, LVDS, CML, HCSL, LVCMOS) • Wide frequency range • Output Enable option • Multiple configuration options • Dual Bank option • 2:1 | SKYWORKS 思佳讯 | |||
Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features Supports single-ended or differential input clock signals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif | SKYWORKS 思佳讯 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features Supports single-ended or differential input clock signals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif | SKYWORKS 思佳讯 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features Supports single-ended or differential input clock signals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif | SKYWORKS 思佳讯 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features Supports single-ended or differential input clock signals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif | SKYWORKS 思佳讯 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features Supports single-ended or differential input clock signals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif | SKYWORKS 思佳讯 | |||
Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features Supports single-ended or differential input clock signals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif | SKYWORKS 思佳讯 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features Supports single-ended or differential input clock signals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif | SKYWORKS 思佳讯 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features Supports single-ended or differential input clock signals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif | SKYWORKS 思佳讯 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features Supports single-ended or differential input clock signals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif | SKYWORKS 思佳讯 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features Supports single-ended or differential input clock signals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif | SKYWORKS 思佳讯 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features Supports single-ended or differential input clock signals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif | SKYWORKS 思佳讯 | |||
Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
Supports single-ended or differential input clock singnals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Features ■ Supports single-ended or differential input clock signals ■ Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs ■ Provides signal level translation ● Differential to single-ended ● Single-ended to differential ● Differential t | SILABS 芯科科技 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features Supports single-ended or differential input clock signals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif | SKYWORKS 思佳讯 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features Supports single-ended or differential input clock signals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif | SKYWORKS 思佳讯 | |||
1.8/2.5/3.3 V LOW-JITTER, LOW-SKEW CLOCK BUFFER/LEVEL TRANSLATOR Features Supports single-ended or differential input clock signals Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) outputs Provides signal level translation Differential to single-ended Single-ended to differential Differential to dif | SKYWORKS 思佳讯 |
SI5330产品属性
- 类型
描述
- 型号
SI5330
- 制造商
Silicon Laboratories Inc
- 功能描述
DUAL
- 1
5 UNIVERSAL BUFFER/LEVEL TRANSLATOR(725MHZ), SYNC. O - Rail/Tube
- 制造商
Silicon Laboratories Inc
- 功能描述
IC TRANSLATOR BUFF/LEVEL 44QFN
- 制造商
Silicon Laboratories Inc
- 1
5 Univrsl transltr 725MHz output enable
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
SILICON LABS/芯科 |
1604+ |
QFN |
2 |
原装正品 可含税交易 |
|||
SILICON |
22+ |
QFN16 |
750 |
只做原装 |
|||
Skyworks |
21+ |
QFN44 |
689 |
全新原装公司现货
|
|||
SILICON |
2021+ |
QFN |
9450 |
原装现货。 |
|||
Silicon Labs |
23+ |
QFN16 |
1500 |
正规渠道,只有原装! |
|||
Skyworks(思佳讯) |
24+ |
标准封装 |
8048 |
支持大陆交货,美金交易。原装现货库存。 |
|||
SILICON/SKYWORKS |
21+ |
2500 |
全新原装鄙视假货 |
||||
SKYWORKS/思佳讯 |
24+ |
QFN24 |
3243 |
原装现货/假一罚十 |
|||
SILICON |
2025+ |
QFN |
5000 |
原装进口,免费送样品! |
|||
SILICON |
20+ |
SMD |
3780 |
只做原装正品假一赔十!正规渠道订货! |
SI5330规格书下载地址
SI5330参数引脚图相关
- sw-262
- stm32f103
- stm32
- stk
- stc89c52rc
- stc12c5a60s2
- st70
- st18
- sst25vf040
- sr2m
- spwm
- spice模型
- spd
- sp3232
- soc
- smd
- sl11
- sk100
- sja1000
- sig
- Si5332A
- SI53325
- SI53323
- SI53322
- SI53321
- SI53320
- SI5332
- SI53315
- SI53314
- SI53313
- SI53312
- SI53311
- SI5330F-B00214-GM
- SI5330C-B00209-GM
- SI5330C-B00208-GM
- SI5330C-B00207-GM
- SI5330B-B00206-GM
- SI5330B-B00205-GM
- SI5330B-B00204-GM
- SI5330A-B00202-GM
- SI5330A-B00200-GM
- SI53308-B-GM
- SI53308
- SI53307-B-GM
- SI53307
- SI53306-B-GM
- SI53306
- SI53305-B-GM
- SI53305
- SI53304-B-GM
- SI53304
- SI53303-B-GM
- SI53303
- SI53302-B-GMR
- SI53302-B-GM
- SI53302
- SI53301-B-GMR
- SI53301-B-GM
- SI53301/4-EVB
- SI53301
- SI533
- SI5328-EVB
- SI5328C-C-GM
- SI5328B-C-GM
- SI5328
- SI5327D-C-GM
- SI5327C-C-GM
- SI5327B-C-GM
- SI5327
- SI5326C-C-GM
- SI5326B-C-GMR
- SI5326B-C-GM
- SI5326A-C-GM
- SI5326
- SI5325C-C-GM
- SI5325B-C-GM
- Si5325
- SI5324-EVB
- SI5324D-C-GM
- SI5324B-C-GM
- SI5324A-C-GM
- Si5324
- SI5323-C-GM
- Si5323
- SI5322
- SI5321-H-GL
- SI5321-H-BL
- SI5321
- SI5320
- Si532
- SI5319
- SI5318
- SI5317-EVB
- SI5317
- SI5316
- SI53159
- SI53156
- SI53154
- SI53152
- SI5315
SI5330数据表相关新闻
Si53159-A01AGM时钟缓冲器
Si53159-A01AGM原装一定原装
2025-7-16SI52147-A01AGMR SILICON/芯科 21+ QFN48
https://hfx03.114ic.com/
2022-1-28SI53340-B-GM
SI53340-B-GM
2021-10-29SI53307-B-GM
SI53307-B-GM
2021-7-30SI5332A-D-GM1
Programmable Clock Generators 时钟发生器及支持产品 , QFN-48 时钟发生器及支持产品 , 333.33 MHz 时钟发生器及支持产品 , 4 Output QFN-24 时钟发生器及支持产品 , 1 Output Clock Generators 时钟发生器及支持产品 , 6 Output 100 MHz 时钟发生器及支持产品
2020-7-8SI5315B-C-GM
Programmable Clock Generators 时钟发生器及支持产品 , QFN-48 时钟发生器及支持产品 , Programmable Clock Generators 时钟发生器及支持产品 , 8 Output 时钟发生器及支持产品 , Programmable Clock Generators 时钟发生器及支持产品 , 350 MHz 时钟发生器及支持产品
2020-7-8
DdatasheetPDF页码索引
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