PRECISION CLOCK MULTIPLIER/REGENERATOR IC

Description The Si5310 is a fully integrated low-power clock multiplier and clock regenerator IC. The clock multiplier generates an output clock that is an integer multiple of the input clock. The clock regenerator operates simultaneously, creating a “clean” version of the input clock by using th

PRECISION CLOCK MULTIPLIER/REGENERATOR IC

PCI-Express Gen 1, Gen 2, Gen 3, and Gen 4 1:2 Fan-out Clock Buffer

KEY FEATURES • PCI-Express Gen 1, Gen 2, Gen 3, and Gen 4 common clock compliant • Two low-power PCIe clock outputs • Supports Serial-ATA (SATA) at 100 MHz • No termination resistors required for differential clocks • 2.5 V or 3.3 V Power supply • Spread Spectrum Tolerant • Extended Tempe

PCI-Express Gen 1, Gen 2, Gen 3, and Gen 4 1:2 Fan-out Clock Buffer

KEY FEATURES • PCI-Express Gen 1, Gen 2, Gen 3, and Gen 4 common clock compliant • Two low-power PCIe clock outputs • Supports Serial-ATA (SATA) at 100 MHz • No termination resistors required for differential clocks • 2.5 V or 3.3 V Power supply • Spread Spectrum Tolerant • Extended Tempe

PCI-Express Gen 1, Gen 2, Gen 3, and Gen 4 1:2 Fan-out Clock Buffer

KEY FEATURES • PCI-Express Gen 1, Gen 2, Gen 3, and Gen 4 common clock compliant • Two low-power PCIe clock outputs • Supports Serial-ATA (SATA) at 100 MHz • No termination resistors required for differential clocks • 2.5 V or 3.3 V Power supply • Spread Spectrum Tolerant • Extended Tempe

PCI-Express Gen 1, Gen 2, Gen 3, and Gen 4 1:2 Fan-out Clock Buffer

KEY FEATURES • PCI-Express Gen 1, Gen 2, Gen 3, and Gen 4 common clock compliant • Two low-power PCIe clock outputs • Supports Serial-ATA (SATA) at 100 MHz • No termination resistors required for differential clocks • 2.5 V or 3.3 V Power supply • Spread Spectrum Tolerant • Extended Tempe

PCI-Express Gen 1, Gen 2, Gen 3, and Gen 4 1:2 Fan-out Clock Buffer

KEY FEATURES • PCI-Express Gen 1, Gen 2, Gen 3, and Gen 4 common clock compliant • Two low-power PCIe clock outputs • Supports Serial-ATA (SATA) at 100 MHz • No termination resistors required for differential clocks • 2.5 V or 3.3 V Power supply • Spread Spectrum Tolerant • Extended Tempe

PCI-Express Gen 1, Gen 2, Gen 3, and Gen 4 1:2 Fan-out Clock Buffer

KEY FEATURES • PCI-Express Gen 1, Gen 2, Gen 3, and Gen 4 common clock compliant • Two low-power PCIe clock outputs • Supports Serial-ATA (SATA) at 100 MHz • No termination resistors required for differential clocks • 2.5 V or 3.3 V Power supply • Spread Spectrum Tolerant • Extended Tempe

PCI-Express Gen 1, Gen 2, Gen 3, and Gen 4 1:2 Fan-out Clock Buffer

KEY FEATURES • PCI-Express Gen 1, Gen 2, Gen 3, and Gen 4 common clock compliant • Two low-power PCIe clock outputs • Supports Serial-ATA (SATA) at 100 MHz • No termination resistors required for differential clocks • 2.5 V or 3.3 V Power supply • Spread Spectrum Tolerant • Extended Tempe

PCI-Express Gen 1, Gen 2, Gen 3, and Gen 4 1:2 Fan-out Clock Buffer

KEY FEATURES • PCI-Express Gen 1, Gen 2, Gen 3, and Gen 4 common clock compliant • Two low-power PCIe clock outputs • Supports Serial-ATA (SATA) at 100 MHz • No termination resistors required for differential clocks • 2.5 V or 3.3 V Power supply • Spread Spectrum Tolerant • Extended Tempe

PCI-Express Gen 1, Gen 2, Gen 3, and Gen 4 1:2 Fan-out Clock Buffer

KEY FEATURES • PCI-Express Gen 1, Gen 2, Gen 3, and Gen 4 common clock compliant • Two low-power PCIe clock outputs • Supports Serial-ATA (SATA) at 100 MHz • No termination resistors required for differential clocks • 2.5 V or 3.3 V Power supply • Spread Spectrum Tolerant • Extended Tempe

SIX-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

Features  Six 0.7 V low-power, push-pull, HCSL-compatible PCIe Gen 3 outputs  Individual OE HW pins for each output clock  100 MHz /133 MHz PLL operation, supports PCIe and QPI  PLL bandwidth SW SMBUS programming overrides the latch value from HW pin  SMBus address configurable to

SIX-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

Features  Six 0.7 V low-power, push-pull, HCSL-compatible PCIe Gen 3 outputs  Individual OE HW pins for each output clock  100 MHz /133 MHz PLL operation, supports PCIe and QPI  PLL bandwidth SW SMBUS programming overrides the latch value from HW pin  SMBus address configurable to

SIX-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

Features  Six 0.7 V low-power, push-pull, HCSL-compatible PCIe Gen 3 outputs  Individual OE HW pins for each output clock  100 MHz /133 MHz PLL operation, supports PCIe and QPI  PLL bandwidth SW SMBUS programming overrides the latch value from HW pin  SMBus address configurable to

DB800ZL 8-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

Features  Eight 0.7 V low-power, push-pull, HCSL-compatible PCIe Gen 3 outputs  Individual OE HW pins for each output clock  100 MHz /133 MHz PLL operation, supports PCIe and QPI  SMBus address is 0xD8  PLL or bypass mode  Spread spectrum tolerable  1.05 to 3.3 V power supply v

DB800ZL 8-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

Features  Eight 0.7 V low-power, push-pull, HCSL-compatible PCIe Gen 3 outputs  Individual OE HW pins for each output clock  100 MHz /133 MHz PLL operation, supports PCIe and QPI  SMBus address is 0xD8  PLL or bypass mode  Spread spectrum tolerable  1.05 to 3.3 V power supply v

DB800ZL 8-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

Features  Eight 0.7 V low-power, push-pull, HCSL-compatible PCIe Gen 3 outputs  Individual OE HW pins for each output clock  100 MHz /133 MHz PLL operation, supports PCIe and QPI  SMBus address is 0xD8  PLL or bypass mode  Spread spectrum tolerable  1.05 to 3.3 V power supply v

PRECISION CLOCK MULTIPLIER/REGENERATOR IC

Description The Si5310 is a fully integrated low-power clock multiplier and clock regenerator IC. The clock multiplier generates an output clock that is an integer multiple of the input clock. The clock regenerator operates simultaneously, creating a “clean” version of the input clock by using th

PRECISION CLOCK MULTIPLIER/REGENERATOR IC

Description The Si5310 is a fully integrated low-power clock multiplier and clock regenerator IC. The clock multiplier generates an output clock that is an integer multiple of the input clock. The clock regenerator operates simultaneously, creating a “clean” version of the input clock by using th

PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 1:2 FAN-OUT CLOCK BUFFER

文件：1.13064 Mbytes Page：15 Pages

PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 1:2 FAN-OUT CLOCK BUFFER

文件：1.13064 Mbytes Page：15 Pages

PCI Express Clock Fanout Buffer Si53102-A2

封装/外壳：8-TDFN 裸露焊盘 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC CLK BUFFER PCIE 1:2 8TDFN 集成电路（IC） 应用特定时钟/定时

PCI Express Clock Fanout Buffer Si53102-A3

PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 1:2 FAN-OUT CLOCK BUFFER

文件：1.13064 Mbytes Page：15 Pages

封装/外壳：8-WFDFN 裸露焊盘 包装：卷带（TR） 描述：IC CLK BUFFER PCIE 1:2 8TDFN 集成电路（IC） 应用特定时钟/定时

SIX-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

文件：1.4211 Mbytes Page：34 Pages

DB800ZL 8-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER

文件：1.46162 Mbytes Page：38 Pages

DC pin controls per data sheet specification

文件：1.49622 Mbytes Page：7 Pages

Simple jumper configuration

文件：1.12438 Mbytes Page：12 Pages

Arista 5000 Series Enterprise WAN Routers

文件：2.93884 Mbytes Page：43 Pages

22 (7/30) AWG Tinned Copper

文件：411.37 Kbytes Page：4 Pages

T-1 LED Circuit Board Indicator

文件：108.53 Kbytes Page：1 Pages

T-1 LED Circuit Board Indicator

文件：71.23 Kbytes Page：1 Pages

2.5 V to 5.5 V, 500 uA, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs

文件：427.29 Kbytes Page：20 Pages