Features

 Six 0.7 V low-power, push-pull,

HCSL-compatible PCIe Gen 3

outputs

 Individual OE HW pins for each

output clock

 100 MHz /133 MHz PLL

operation, supports PCIe and

QPI

 PLL bandwidth SW SMBUS

programming overrides the latch

value from HW pin

 SMBus address configurable to

allow multiple buffers in a single

control network 3.3 V supply

voltage operation

 Low phase jitter (Intel QPI, PCIe

Gen 1/2/3/4 common clock

compliant

 Gen 3 SRNS Compliant

 PLL or bypass mode

 Spread spectrum tolerable

 1.05 to 3.3 V I/O supply voltage

 50 ps output-to-output skew

 Industrial Temperature:

–40 to 85 °C

 40-pin QFN

 For higher output devices or

variations of this device, contact

Skyworks Solutions