General purpose chip resistors

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Standard chip resistors

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VersaClock 7 Programmable Jitter Attenuator Family

Features ▪ 169fs RMS typical phase jitter ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ▪ Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs

VersaClock 7 Programmable Jitter Attenuator Family

Features ▪ 169fs RMS typical phase jitter ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ▪ Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs

VersaClock 7 Programmable Jitter Attenuator Family

Features ▪ 169fs RMS typical phase jitter ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ▪ Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs

VersaClock 7 Programmable Jitter Attenuator Family

Features ▪ 169fs RMS typical phase jitter ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ▪ Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs

VersaClock 7 Programmable Jitter Attenuator Family

Features ▪ 169fs RMS typical phase jitter ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ▪ Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs

VersaClock 7 Programmable Jitter Attenuator Family

Features ▪ 169fs RMS typical phase jitter ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ▪ Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs

VersaClock 7 Programmable Jitter Attenuator Family

Features ▪ 169fs RMS typical phase jitter ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ▪ Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs

VersaClock 7 Programmable Jitter Attenuator Family

Features ▪ 169fs RMS typical phase jitter ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ▪ Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs

VersaClock 7 Programmable Jitter Attenuator Family

Features ▪ 169fs RMS typical phase jitter ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ▪ Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs

VersaClock 7 Programmable Jitter Attenuator Family

Features ▪ 169fs RMS typical phase jitter ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ▪ Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs

VersaClock 7 Programmable Jitter Attenuator Family

Features ▪ 169fs RMS typical phase jitter ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ▪ Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs

VersaClock 7 Programmable Jitter Attenuator Family

Features ▪ 169fs RMS typical phase jitter ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ▪ Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs

VersaClock 7 Programmable Jitter Attenuator Family

Features ▪ 169fs RMS typical phase jitter ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ▪ Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs

VersaClock 7 Programmable Jitter Attenuator Family

Features ▪ 169fs RMS typical phase jitter ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ▪ Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs

VersaClock 7 Programmable Jitter Attenuator Family

Features ▪ 169fs RMS typical phase jitter ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ▪ Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs

VersaClock 7 Programmable Jitter Attenuator Family

Features ▪ 169fs RMS typical phase jitter ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ▪ Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs

VersaClock 7 Programmable Jitter Attenuator Family

Features ▪ 169fs RMS typical phase jitter ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ Compliant with ITU-T G.8262 and G.8262.1 for synchronous Ethernet Equipment Clock (EEC/eEEC) ▪ Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs

SINGLE-PHASE SILICON BRIDGE RECTIFIER

文件：40.26 Kbytes Page：1 Pages

VersaClock® 7 可编程抖动衰减器系列

包装：卷带（TR） 描述：IC CLOCK JITTER PCIE 40VFQFPN 集成电路（IC） 时钟发生器，PLL，频率合成器

包装：卷带（TR） 描述：IC CLOCK JITTER PCIE 40VFQFPN 集成电路（IC） 时钟发生器，PLL，频率合成器

Molded Metal Film Resistors

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