AAL1 Segmentation And Reassembly Processor

Description The AAL1 Segmentation And Reassembly (SAR) Processor (AAL1gator II™) provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage of the configuration, the user data,

AAL1 Segmentation And Reassembly Processor

Description The AAL1 Segmentation And Reassembly (SAR) Processor (AAL1gator II™) provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage of the configuration, the user data,

32 LINK CES/DBCES AAL1 SAR PROCESSOR

DESCRIPTION The AAL1 Segmentation And Reassembly (SAR) Processor (AAL1gator-32) is a monolithic single chip device that provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storag

32 LINK CES/DBCES AAL1 SAR PROCESSOR

DESCRIPTION The AAL1 Segmentation And Reassembly (SAR) Processor (AAL1gator-32) is a monolithic single chip device that provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storag

8 LINK CES/DBCES AAL1 SAR

DESCRIPTION The AAL1gator-8 AAL1 Segmentation And Reassembly (SAR) Processor is a monolithic single chip device that provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage o

8 LINK CES/DBCES AAL1 SAR

DESCRIPTION The AAL1gator-8 AAL1 Segmentation And Reassembly (SAR) Processor is a monolithic single chip device that provides DS1, E1, E3, or DS3 line interface access to an ATM Adaptation Layer One (AAL1) Constant Bit Rate (CBR) ATM network. It arbitrates access to an external SRAM for storage o

4 Link CES/DBCES AAL1 SAR

FEATURES • Supports four structured/unstructured T1 or E1 links, or one unstructured DS3, E3 or STS-1/STM-0 link over an AAL1 CBR ATM network. • Compliant with ATM Forums CES (AFVTOA-0078), and ITU-T I.363.1. • Supports up to 128 VCs. • Supports n x 64 (consecutive channels) an

电信接口IC 336 Link, 1024 Channel HDLC Controller with FR and PPP Multilink, and Low Latency support

电信接口IC 84 Link, 1024 Channel HDLC Controller with FR and PPP Multilink, and Low Latency support

AAL1 Segmentation And Reassembly Processor

8 Link CES/DBCES AAL1 SAR

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Ultra quiet, ultra low-frequency accelerometer

Key features • Ultra low-noise electronics for clear signals at sub-μg levels • Ultra high sensitivity • Manufactured in ISO 9001 facility

16-/32- Channel, Serially Controlled 4 ??1.8 V to 5.5 V, 짹2.5 V, Analog Multiplexers

GENERAL DESCRIPTION The ADG725/ADG731 are monolithic CMOS 32 channel/dual 16 channel analog multiplexers with a serially controlled 3-wire interface. The ADG732 switches one of thirty-two inputs (S1-S32) to a common output, D. The ADG725 can be configured as a dual mux switching one of sixteen

16-/32-Channel, Serially Controlled 4,
1.8 V to 5.5 V, 2.5 V, Analog Multiplexers

GENERAL DESCRIPTION The ADG725/ADG731 are monolithic CMOS 32 channel/dual 16 channel analog multiplexers with a serially controlled 3-wire interface. The ADG732 switches one of thirty-two inputs (S1-S32) to a common output, D. The ADG725 can be configured as a dual mux switching one of sixteen

16-/32-Channel, Serially Controlled 4
1.8 V to 5.5 V, 2.5 V, Analog Multiplexers

文件：362.37 Kbytes Page：16 Pages

16-/32-Channel, Serially Controlled

文件：362.37 Kbytes Page：16 Pages