3.3-V DUAL PLL MULTICLOCK GENERATOR

FEATURES 27-MHz Master Clock Input Generated Audio System Clock: − SCKO0: 768 fS (fS = 44.1 kHz) − SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) − SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) − SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Zero PPM Error Output Clocks Low Clock Jitt

3.3-V DUAL PLL MULTICLOCK GENERATOR

文件：128.13 Kbytes Page：17 Pages

3.3-V DUAL PLL MULTICLOCK GENERATOR

文件：157.81 Kbytes Page：18 Pages

封装/外壳：20-SSOP（0.154"，3.90mm 宽） 包装：带 描述：IC MLT-CLK GENERATR DUAL 20-QSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3-V DUAL PLL MULTICLOCK GENERATOR

FEATURES 27-MHz Master Clock Input Generated Audio System Clock: − SCKO0: 768 fS (fS = 44.1 kHz) − SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) − SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) − SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Zero PPM Error Output Clocks Low Clock Jitt

3.3-V DUAL PLL MULTICLOCK GENERATOR

FEATURES 27-MHz Master Clock Input Generated Audio System Clock: − SCKO0: 768 fS (fS = 44.1 kHz) − SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) − SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) − SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Zero PPM Error Output Clocks Low Clock Jitt

3.3-V DUAL PLL MULTICLOCK GENERATOR

FEATURES 27-MHz Master Clock Input Generated Audio System Clock: − SCKO0: 768 fS (fS = 44.1 kHz) − SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) − SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) − SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Zero PPM Error Output Clocks Low Clock Jitt

3.3-V DUAL PLL MULTICLOCK GENERATOR

FEATURES 27-MHz Master Clock Input Generated Audio System Clock: − SCKO0: 768 fS (fS = 44.1 kHz) − SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) − SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) − SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Zero PPM Error Output Clocks Low Clock Jitt

3.3-V DUAL PLL MULTICLOCK GENERATOR

文件：157.81 Kbytes Page：18 Pages

封装/外壳：20-SSOP（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC PLL MULTI-CLK GEN DUAL 20QSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3-V DUAL PLL MULTICLOCK GENERATOR

文件：157.81 Kbytes Page：18 Pages

3.3-V DUAL PLL MULTICLOCK GENERATOR

文件：128.13 Kbytes Page：17 Pages

3.3-V DUAL PLL MULTICLOCK GENERATOR

文件：157.81 Kbytes Page：18 Pages

Customer Specification

Construction Diameters (In) 1) Component 1 1 X 1 COND a) Conductor 20 (26/34) AWG Tinned Copper 0.038 b) Insulation 0.031 Wall, Nom. Polyethylene(PE) 0.100 (1) Color(s) Cond Color Cond Color Cond Color 1 WHITE 2) Shield Tinned Copper BRAID Shield,90 Coverage, Min. 3) Jacket 0.030 Wall,

1 A, Low Dropout, CMOS Linear Regulator

GENERAL DESCRIPTION The ADP1706/ADP1707/ADP1708 are CMOS, low dropout linear regulators that operate from 2.5 V to 5.5 V and provide up to 1 A of output current. Using an advanced proprietary architecture, they provide high power supply rejection and achieve excellent line and load transient resp

1 A, Low Dropout, CMOS Linear Regulator

GENERAL DESCRIPTION The ADP1706/ADP1707/ADP1708 are CMOS, low dropout linear regulators that operate from 2.5 V to 5.5 V and provide up to 1 A of output current. Using an advanced proprietary architecture, they provide high power supply rejection and achieve excellent line and load transient resp

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