T1/E1 Synchronizer

Description The MT9040 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for T1 and E1 primary rate transmission links. Features • Supports AT&T TR62411 and Bellcore GR-1244- CORE and Stratum 4 timing for DS1 interfaces

SONET/SDH System Synchronizer

Description The MT90401 is a digital phase locked loop (DPLL) that is designed to synchronize SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The MT90401 is used to ensure that the timing of outgoing signals remains within the limits specified by

SONET/SDH System Synchronizer

Description The MT90401 is a digital phase locked loop (DPLL) that is designed to synchronize SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The MT90401 is used to ensure that the timing of outgoing signals remains within the limits specified by

SONET/SDH System Synchronizer

Description The MT90401 is a digital phase locked loop (DPLL) that is designed to synchronize SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The MT90401 is used to ensure that the timing of outgoing signals remains within the limits specified by

T1/E1 Synchronizer

Description The MT9040 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for T1 and E1 primary rate transmission links. Features • Supports AT&T TR62411 and Bellcore GR-1244- CORE and Stratum 4 timing for DS1 interfaces

Multiple Output Trunk PLL

Description The MT9041 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1.

Multiple Output Trunk PLL

Description The MT9041 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1.

T1/E1 System Synchronizer

Description The MT9041B T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9041B generates ST-BUS clock and framing signals that are phase locked to either a

T1/E1 System Synchronizer

Description The MT9041B T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9041B generates ST-BUS clock and framing signals that are phase locked to either a

Global Digital Trunk Synchronizer

Description The MT9042 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1.

Global Digital Trunk Synchronizer

Description The MT9042 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1.

Multitrunk System Synchronizer

Description The MT9042C Multitrunk System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9042C generates ST-BUS clock and framing signals that are phase locked to eith

Multitrunk System Synchronizer

Description The MT9042C Multitrunk System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9042C generates ST-BUS clock and framing signals that are phase locked to eith

T1/E1 System Synchronizer

Description The MT9043 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. Features • Supports AT&T TR62411 and Bellcore GR-1244-CORE, Stratum 4 Enhanced and Stratu

T1/E1 System Synchronizer

Description The MT9043 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. Features • Supports AT&T TR62411 and Bellcore GR-1244-CORE, Stratum 4 Enhanced and Stratu

T1/E1 System Synchronizer

Description The MT9043 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. Features • Supports AT&T TR62411 and Bellcore GR-1244-CORE, Stratum 4 Enhanced and Stratu

T1/E1/OC3 System Synchronizer

Description The MT9044 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/0C3 links. Features • Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratu

T1/E1/OC3 System Synchronizer

Description The MT9044 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/0C3 links. Features • Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratu

T1/E1/OC3 System Synchronizer

Description The MT9044 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/0C3 links. Features • Supports AT&T TR62411 and Bellcore GR-1244-CORE Stratu

T1/E1/OC3 System Synchronizer

Description The MT9045 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/OC3 links. The MT9045 generates ST-BUS clock and framing signals that are

T1/E1/OC3 System Synchronizer

Description The MT9045 T1/E1/OC3 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links and STS-3/OC3 links. The MT9045 generates ST-BUS clock and framing signals that are

T1/E1 System Synchronizer with Holdover

Description The MT9046 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The device has reference switching and frequency holdover capabilities to help maintain connect

T1/E1 System Synchronizer with Holdover

Description The MT9046 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The device has reference switching and frequency holdover capabilities to help maintain connect

SONET/SDH Clock Multiplier PLL

文件：249.12 Kbytes Page：21 Pages

SONET/SDH System Synchronizer

SONET/SDH system synchronizer.

T1/E1 Synchronizer

封装/外壳：48-SSOP（0.295"，7.50mm 宽） 功能：数字锁相环 包装：卷带（TR） 描述：IC TELECOM INTERFACE 48SSOP 集成电路（IC） 电信

封装/外壳：48-BSSOP（0.295"，7.50mm 宽） 功能：数字锁相环 包装：卷带（TR） 描述：IC TELECOM INTERFACE 48SSOP 集成电路（IC） 电信

SONET/SDH Clock Multiplier PLL

文件：404.85 Kbytes Page：23 Pages

SONET/SDH Clock Multiplier PLL

文件：249.12 Kbytes Page：21 Pages

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