Multiple Output Trunk PLL

Description The MT9041 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1.

T1/E1 System Synchronizer

Multiple Output Trunk PLL

Description The MT9041 is a digital phase-locked loop (PLL) designed to provide timing and synchronization signals for T1 and E1 primary rate transmission links that are compatible with ST-BUS/GCI frame alignment timing requirements. The PLL outputs can be synchronized to either a 2.048 MHz, 1.

T1/E1 System Synchronizer

Description The MT9041B T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9041B generates ST-BUS clock and framing signals that are phase locked to either a

T1/E1 System Synchronizer

Description The MT9041B T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization signals for multitrunk T1 and E1 primary rate transmission links. The MT9041B generates ST-BUS clock and framing signals that are phase locked to either a

T1/E1 System Synchronizer

T1/E1 System Synchronizer

封装/外壳：28-LCC（J 形引线） 功能：数字锁相环 包装：托盘 描述：IC TELECOM INTERFACE 28PLCC 集成电路（IC） 电信

封装/外壳：28-LCC（J 形引线） 功能：数字锁相环 包装：卷带（TR） 描述：IC TELECOM INTERFACE 28PLCC 集成电路（IC） 电信

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