Dual D Flip-Flop with Set and Reset

Dual D Flip−Flop with Set and Reset High−Performance Silicon−Gate CMOS The MC74HC74A is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip−flops with indi

Dual D Flip?묯lop with Set and Reset High?뭁erformance Silicon?묰ate CMOS

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Dual D Flip?묯lop with Set and Reset High?뭁erformance Silicon?묰ate CMOS

文件：179.41 Kbytes Page：9 Pages

Dual D Flip-Flop with Set and Reset

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封装/外壳：14-DIP（0.300"，7.62mm） 功能：设置（预设）和复位 包装：卷带（TR） 描述：IC FF D-TYPE DUAL 1BIT 14DIP 集成电路（IC） 触发器

Dual D Flip?묯lop with Set and Reset High?뭁erformance Silicon?묰ate CMOS

The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip−flops with individual Set, Reset, and Clock inputs. Information at a D−input is transferred

Dual D-type flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: flip-flops

Dual D-type flip-flop with set and reset; positive edge-trigger

1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-

High Speed CMOS Logic

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Dual D-type flip-flop with set and reset; positive edge-trigger

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