Dual D Flip?묯lop with Set and Reset High?뭁erformance Silicon?묰ate CMOS

The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip−flops with individual Set, Reset, and Clock inputs. Information at a D−input is transferred

Dual D-type flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: flip-flops

Dual D-type flip-flop with set and reset; positive edge-trigger

1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-

Dual D-type flip-flop with set and reset; positive edge-trigger

Dual D-type flip-flop with set and reset; positive edge-trigger

High Speed CMOS Logic

Features Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Low Input Current: 1μA Asynchronous Set-Reset Capability ±4mA Output Drive at 5V Operating Voltage Range: 2.0 to 6.0 V Direct drop-in replacement for obsolete components in long term programs

High Speed CMOS Logic

文件：467.12 Kbytes Page：6 Pages

Dual D-type flip-flop with set and reset; positive edge-trigger

文件：175.47 Kbytes Page：21 Pages

High Speed CMOS Logic

文件：791.12 Kbytes Page：6 Pages

High Speed CMOS Logic

Features Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Low Input Current: 1μA Asynchronous Set-Reset Capability ±4mA Output Drive at 5V Operating Voltage Range: 2.0 to 6.0 V Direct drop-in replacement for obsolete components in long term programs

4-Bit x 64-word FIFO register; 3-state

GENERAL DESCRIPTION The 74HC/HCT7403 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no.7A. FEATURES • Synchronous or asynchronous operation • 3-state outputs • 30 MHz (typical) shift-in and shift-out rates • Readily expandable in word

4-Bit x 64-word FIFO register; 3-state

GENERAL DESCRIPTION The 74HC/HCT7403 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no.7A. FEATURES • Synchronous or asynchronous operation • 3-state outputs • 30 MHz (typical) shift-in and shift-out rates • Readily expandable in word

4-Bit x 64-word FIFO register; 3-state

GENERAL DESCRIPTION The 74HC/HCT7403 are high-speed Si-gate CMOS devices. They are specified in compliance with JEDEC standard no.7A. FEATURES • Synchronous or asynchronous operation • 3-state outputs • 30 MHz (typical) shift-in and shift-out rates • Readily expandable in word

5-Bit x 64-word FIFO register; 3-state

GENERAL DESCRIPTION The 74HC/HCT7404 are high-speed Si-gate CMOS devices specified in compliance with JEDEC standard no.7A. The “7404” is an expandable, First-In First-Out (FIFO) memory organized as 64 words by 5 bits. A guaranteed 15 MHz data-rate makes it ideal for high-speed applications.

5-Bit x 64-word FIFO register; 3-state

GENERAL DESCRIPTION The 74HC/HCT7404 are high-speed Si-gate CMOS devices specified in compliance with JEDEC standard no.7A. The “7404” is an expandable, First-In First-Out (FIFO) memory organized as 64 words by 5 bits. A guaranteed 15 MHz data-rate makes it ideal for high-speed applications.

5-Bit x 64-word FIFO register; 3-state

GENERAL DESCRIPTION The 74HC/HCT7404 are high-speed Si-gate CMOS devices specified in compliance with JEDEC standard no.7A. The “7404” is an expandable, First-In First-Out (FIFO) memory organized as 64 words by 5 bits. A guaranteed 15 MHz data-rate makes it ideal for high-speed applications.

Dual D-Type Flip Flop Preset and Clear

Features • High speed: fmax = 77 MHz (typ.) at VCC = 5 V • Low power dissipation: ICC = 2 µA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28 VCC (min) • Output drive capability: 10 LSTTL loads • Symmetrical output impedance: |IOH| = IOL = 4 mA (min) • Balanced propagation delays:

Dual D-type flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: flip-flops

Dual D-type flip-flop with set and reset; positive edge-trigger

Dual D-type flip-flop with set and reset; positive edge-trigger

1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-

Dual D-type flip-flop with set and reset; positive edge-trigger

1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-

Dual D-type flip-flop with set and reset; positive edge-trigger

1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-

Dual D-type flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: flip-flops

Dual D Flip?묯lop with Set and Reset High?뭁erformance Silicon?묰ate CMOS

The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip−flops with individual Set, Reset, and Clock inputs. Information at a D−input is transferred

CMOS Digital Integrated Circuits Silicon Monolithic

Functional Description • Dual D-Type Flip-Flop with Preset and Clear General The 74HC74D is a high speed CMOS D FLIP FLOP fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The sign

Dual D-type flip-flop with set and reset; positive edge-trigger

Dual D-type flip-flop with set and reset; positive edge-trigger

Dual D-type flip-flop with set and reset; positive edge-trigger

Dual D-type flip-flop with set and reset; positive edge-trigger

Dual D-type flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: flip-flops

Dual D Flip?묯lop with Set and Reset High?뭁erformance Silicon?묰ate CMOS

The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip−flops with individual Set, Reset, and Clock inputs. Information at a D−input is transferred

Dual D Flip?묯lop with Set and Reset High?뭁erformance Silicon?묰ate CMOS

The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip−flops with individual Set, Reset, and Clock inputs. Information at a D−input is transferred

Dual D Flip?묯lop with Set and Reset High?뭁erformance Silicon?묰ate CMOS

The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip−flops with individual Set, Reset, and Clock inputs. Information at a D−input is transferred

Dual D-type flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: flip-flops

Dual D Flip?묯lop with Set and Reset High?뭁erformance Silicon?묰ate CMOS

The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip−flops with individual Set, Reset, and Clock inputs. Information at a D−input is transferred

Dual D Flip?묯lop with Set and Reset High?뭁erformance Silicon?묰ate CMOS

The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip−flops with individual Set, Reset, and Clock inputs. Information at a D−input is transferred

Dual D-type flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: flip-flops

Dual D-type flip-flop with set and reset; positive edge-trigger

Dual D-type flip-flop with set and reset; positive edge-trigger

Dual D-type flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Output capability: standard • ICC category: flip-flops

Dual D-type flip-flop with set and reset; positive edge-trigger

1. General description The 74HC74 and 74HCT74 are dual positive edge triggered D-type flip-flop. They have individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQ outputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-

Dual D-type flip-flop with set and reset; positive edge-trigger

High Speed CMOS Logic

文件：791.12 Kbytes Page：6 Pages

封装/外壳：16-SOIC（0.295"，7.50mm 宽） 功能：异步，同步 包装：托盘 描述：IC FIFO REGISTER 64X4 16SOIC 集成电路（IC） FIFO 存储器

封装/外壳：16-SOIC（0.295"，7.50mm 宽） 功能：异步，同步 包装：托盘 描述：IC FIFO REGISTER 4X64 3ST 16SOIC 集成电路（IC） FIFO 存储器

4-bit x 64-word FIFO register; 3-state

Dual D Flip-Flop with Set and Reset

文件：116.7 Kbytes Page：7 Pages

Dual D-Type Flip Flop Preset and Clear

文件：234.14 Kbytes Page：9 Pages

CMOS Digital Integrated Circuit Silicon Monolithic Dual D-Type Flip Flop Preset and Clear

文件：312.68 Kbytes Page：10 Pages

DUAL D-TYPE FLIP FLOP PRESET AND CLEAR

文件：236.41 Kbytes Page：6 Pages

Dual D-type flip-flop with set and reset; positive edge-trigger

文件：175.47 Kbytes Page：21 Pages

Dual D-type flip-flop with set and reset; positive edge-trigger

文件：193.4 Kbytes Page：22 Pages

Dual D-type flip-flop with set and reset; positive edge-trigger

文件：798.65 Kbytes Page：19 Pages

Dual D-type flip-flop with set and reset; positive edge-trigger

文件：175.47 Kbytes Page：21 Pages

Dual D-type flip-flop with set and reset; positive edge-trigger

文件：193.4 Kbytes Page：22 Pages

Dual D-type flip-flop with set and reset; positive edge-trigger

文件：193.4 Kbytes Page：22 Pages

Dual D-type flip-flop with set and reset; positive edge-trigger

文件：175.47 Kbytes Page：21 Pages

Dual D-type flip-flop with set and reset; positive edge-trigger

文件：175.47 Kbytes Page：21 Pages

Dual D-type flip-flop with set and reset; positive edge-trigger

文件：798.65 Kbytes Page：19 Pages

Dual D-type flip-flop with set and reset; positive-edge trigger