MC100EP价格

参考价格:¥88.1682

型号:MC100EP016AFAG 品牌:ONSemi 备注:这里有MC100EP多少钱,2025年最近7天走势,今日出价,今日竞价,MC100EP批发/采购报价,MC100EP行情走势销售排行榜,MC100EP报价。
型号 功能描述 生产厂家 企业 LOGO 操作

3.3V / 5VECL 8-Bit Synchronous Binary Up Counter

Description The MC10/100EP016 is a high-speed synchronous, presettable, cascadeable 8-bit binary counter. Architecture and operation are the same as the MC10E016 in the ECLinPS™ family. Features • 500 ps Typical Propagation Delay • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V

ONSEMI

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Clock Management Design Using Low Skew and Low Jitter Devices

Why Do We Need Clock Management? Can you imagine the chaos in our world if our clocks or watches were not synchronized to Greenwich Mean Time? How would trains, buses, and airplanes run on schedule? The miniseries Longitude was the story of a man who made a major technological breakthrough by inv

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3.3V / 5VECL 8-Bit Synchronous Binary Up Counter

Description The MC10/100EP016 is a high-speed synchronous, presettable, cascadeable 8-bit binary counter. Architecture and operation are the same as the MC10E016 in the ECLinPS™ family. Features • 500 ps Typical Propagation Delay • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V

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3.3V / 5VECL 8-Bit Synchronous Binary Up Counter

Description The MC10/100EP016 is a high-speed synchronous, presettable, cascadeable 8-bit binary counter. Architecture and operation are the same as the MC10E016 in the ECLinPS™ family. Features • 500 ps Typical Propagation Delay • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V

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3.3V / 5V ECL 4-Input OR/NOR

The MC10EP01 is a 4−input OR/NOR gate. The device is functionally equivalent to the EL01 device, LVEL01, and E101 (a quad version). With AC performance much faster than the LVEL01 device, the EP01 is ideal for applications requiring the fastest AC performance available. The 100 Series contains te

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3.3V / 5V ECL 4-Input OR/NOR

The MC10EP01 is a 4−input OR/NOR gate. The device is functionally equivalent to the EL01 device, LVEL01, and E101 (a quad version). With AC performance much faster than the LVEL01 device, the EP01 is ideal for applications requiring the fastest AC performance available. The 100 Series contains te

ONSEMI

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3.3V / 5V ECL 4-Input OR/NOR

The MC10EP01 is a 4−input OR/NOR gate. The device is functionally equivalent to the EL01 device, LVEL01, and E101 (a quad version). With AC performance much faster than the LVEL01 device, the EP01 is ideal for applications requiring the fastest AC performance available. The 100 Series contains te

ONSEMI

安森美半导体

3.3V / 5V ECL 4-Input OR/NOR

The MC10EP01 is a 4−input OR/NOR gate. The device is functionally equivalent to the EL01 device, LVEL01, and E101 (a quad version). With AC performance much faster than the LVEL01 device, the EP01 is ideal for applications requiring the fastest AC performance available. The 100 Series contains te

ONSEMI

安森美半导体

3.3V / 5V ECL 2-Input Differential AND/NAND

Description The MC10/100EP05 is a 2−input differential AND/NAND gate. The device is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP05 is ideal for applications requiring the fastest AC performance available. The 100 Series co

ONSEMI

安森美半导体

3.3V / 5V ECL 2-Input Differential AND/NAND

Description The MC10/100EP05 is a 2−input differential AND/NAND gate. The device is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP05 is ideal for applications requiring the fastest AC performance available. The 100 Series co

ONSEMI

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3.3V / 5V ECL 2-Input Differential AND/NAND

Description The MC10/100EP05 is a 2−input differential AND/NAND gate. The device is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP05 is ideal for applications requiring the fastest AC performance available. The 100 Series co

ONSEMI

安森美半导体

3.3V / 5V ECL 2-Input Differential AND/NAND

Description The MC10/100EP05 is a 2−input differential AND/NAND gate. The device is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP05 is ideal for applications requiring the fastest AC performance available. The 100 Series co

ONSEMI

安森美半导体

3.3V / 5V ECL 2-Input Differential AND/NAND

Description The MC10/100EP05 is a 2−input differential AND/NAND gate. The device is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP05 is ideal for applications requiring the fastest AC performance available. The 100 Series co

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3.3V / 5V ECL 2-Input Differential XOR/XNOR

Description The MC10/100EP08 is a differential XOR/XNOR gate. The EP08 is ideal for applications requiring the fastest AC performance available. The 100 Series contains temperature compensation. Features • 250 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Opera

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3.3V / 5V ECL 2-Input Differential XOR/XNOR

Description The MC10/100EP08 is a differential XOR/XNOR gate. The EP08 is ideal for applications requiring the fastest AC performance available. The 100 Series contains temperature compensation. Features • 250 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Opera

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Differential 2-Input XOR/XNOR

Description The MC10/100EP08 is a differential XOR/XNOR gate. The EP08 is ideal for applications requiring the fastest AC performance available. The 100 Series contains temperature compensation. Features • 250 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Opera

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3.3V / 5V ECL 2-Input Differential XOR/XNOR

Description The MC10/100EP08 is a differential XOR/XNOR gate. The EP08 is ideal for applications requiring the fastest AC performance available. The 100 Series contains temperature compensation. Features • 250 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Opera

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Differential 2-Input XOR/XNOR

Description The MC10/100EP08 is a differential XOR/XNOR gate. The EP08 is ideal for applications requiring the fastest AC performance available. The 100 Series contains temperature compensation. Features • 250 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Opera

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Differential 2-Input XOR/XNOR

Description The MC10/100EP08 is a differential XOR/XNOR gate. The EP08 is ideal for applications requiring the fastest AC performance available. The 100 Series contains temperature compensation. Features • 250 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Opera

ONSEMI

安森美半导体

Differential 2-Input XOR/XNOR

Description The MC10/100EP08 is a differential XOR/XNOR gate. The EP08 is ideal for applications requiring the fastest AC performance available. The 100 Series contains temperature compensation. Features • 250 ps Typical Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Opera

ONSEMI

安森美半导体

3.3V / 5V ECL Quad 2-Input Differential AND/NAND

Description The MC10/100EP105 is a quad 2−input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP105 is ideal for applications requiring the fastest AC performance available. The 100 Ser

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3.3V / 5V ECL Quad 2-Input Differential AND/NAND

Description The MC10/100EP105 is a quad 2−input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP105 is ideal for applications requiring the fastest AC performance available. The 100 Ser

ONSEMI

安森美半导体

3.3V / 5V ECL Quad 2-Input Differential AND/NAND

Description The MC10/100EP105 is a quad 2−input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP105 is ideal for applications requiring the fastest AC performance available. The 100 Ser

ONSEMI

安森美半导体

3.3V / 5V ECL Quad 2-Input Differential AND/NAND

Description The MC10/100EP105 is a quad 2−input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP105 is ideal for applications requiring the fastest AC performance available. The 100 Ser

ONSEMI

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3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock

Description The MC10/100EP131 is a Quad Master−slaved D flip−flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables. With AC performance faster than the E131 device, the EP131 is ideal for applications requiring

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3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock

Description The MC10/100EP131 is a Quad Master−slaved D flip−flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables. With AC performance faster than the E131 device, the EP131 is ideal for applications requiring

ONSEMI

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3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock

Description The MC10/100EP131 is a Quad Master−slaved D flip−flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables. With AC performance faster than the E131 device, the EP131 is ideal for applications requiring

ONSEMI

安森美半导体

첨2/4, 첨4./5/6 Clock Generation Chip

Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a di

ONSEMI

安森美半导体

Clock Management Design Using Low Skew and Low Jitter Devices

Why Do We Need Clock Management? Can you imagine the chaos in our world if our clocks or watches were not synchronized to Greenwich Mean Time? How would trains, buses, and airplanes run on schedule? The miniseries Longitude was the story of a man who made a major technological breakthrough by inv

ONSEMI

安森美半导体

3.3V / 5V ECL /2/4, /4/5/6 Clock Generation Chip

Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a di

ONSEMI

安森美半导体

첨2/4, 첨4./5/6 Clock Generation Chip

Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a di

ONSEMI

安森美半导体

첨2/4, 첨4./5/6 Clock Generation Chip

Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a di

ONSEMI

安森美半导体

3.3V / 5V ECL /2/4, /4/5/6 Clock Generation Chip

Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a di

ONSEMI

安森美半导体

3.3V / 5V ECL /2/4, /4/5/6 Clock Generation Chip

Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a di

ONSEMI

安森美半导体

첨2/4, 첨4./5/6 Clock Generation Chip

Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a di

ONSEMI

安森美半导体

첨2/4, 첨4./5/6 Clock Generation Chip

Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a di

ONSEMI

安森美半导体

3.3V / 5V ECL /2/4, /4/5/6 Clock Generation Chip

Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a di

ONSEMI

安森美半导体

3.3 V / 5 V ECL 9-Bit Shift Register

3.3 V / 5 V ECL 9−Bit Shift Register The MC10EP/100EP142 is a 9−bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in only one direction. The nine inputs D0 − D8 accept parallel

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3.3 V / 5 V ECL 9-Bit Shift Register

3.3 V / 5 V ECL 9−Bit Shift Register The MC10EP/100EP142 is a 9−bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in only one direction. The nine inputs D0 − D8 accept parallel

ONSEMI

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3.3 V / 5 V ECL 9-Bit Shift Register

3.3 V / 5 V ECL 9−Bit Shift Register The MC10EP/100EP142 is a 9−bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in only one direction. The nine inputs D0 − D8 accept parallel

ONSEMI

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3.3 V / 5 V ECL 9-Bit Shift Register

3.3 V / 5 V ECL 9−Bit Shift Register The MC10EP/100EP142 is a 9−bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in only one direction. The nine inputs D0 − D8 accept parallel

ONSEMI

安森美半导体

3.3 V / 5 V ECL 9-Bit Shift Register

3.3 V / 5 V ECL 9−Bit Shift Register The MC10EP/100EP142 is a 9−bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in only one direction. The nine inputs D0 − D8 accept parallel

ONSEMI

安森美半导体

3.3 V / 5 V ECL 9-Bit Shift Register

3.3 V / 5 V ECL 9−Bit Shift Register The MC10EP/100EP142 is a 9−bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in only one direction. The nine inputs D0 − D8 accept parallel

ONSEMI

安森美半导体

Clock Management Design Using Low Skew and Low Jitter Devices

Why Do We Need Clock Management? Can you imagine the chaos in our world if our clocks or watches were not synchronized to Greenwich Mean Time? How would trains, buses, and airplanes run on schedule? The miniseries Longitude was the story of a man who made a major technological breakthrough by inv

ONSEMI

安森美半导体

3.3V / 5V ECL Differential Receiver/Driver with Internal Termination

Description The EP16T is a world−class differential receiver/driver. The device is functionally equivalent to the EP16 with internal termination resistors. A 50  resistor is connected from the D input to the VT pin and from the D input to the VT pin. Tie the VT and VT pins to VTT supply (VCC −

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3.3V / 5V ECL Differential Receiver/Driver with Internal Termination

Description The EP16T is a world−class differential receiver/driver. The device is functionally equivalent to the EP16 with internal termination resistors. A 50  resistor is connected from the D input to the VT pin and from the D input to the VT pin. Tie the VT and VT pins to VTT supply (VCC −

ONSEMI

安森美半导体

3.3V / 5V ECL Differential Receiver/Driver with Internal Termination

Description The EP16T is a world−class differential receiver/driver. The device is functionally equivalent to the EP16 with internal termination resistors. A 50  resistor is connected from the D input to the VT pin and from the D input to the VT pin. Tie the VT and VT pins to VTT supply (VCC −

ONSEMI

安森美半导体

3.3V / 5V ECL Differential Receiver/Driver with Internal Termination

Description The EP16T is a world−class differential receiver/driver. The device is functionally equivalent to the EP16 with internal termination resistors. A 50  resistor is connected from the D input to the VT pin and from the D input to the VT pin. Tie the VT and VT pins to VTT supply (VCC −

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3.3V / 5VECL Differential Receiver/Driver with High Gain

Description The EP16VA is a world−class differential receiver/driver. The device is functionally equivalent to the EP16 and LVEP16 devices but with high gain output. QHG and QHG outputs have a DC gain several times larger than the DC gain of an EP16. The VBB pin, an internally generated volt

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3.3V / 5VECL Differential Receiver/Driver with High Gain

Description The EP16VA is a world−class differential receiver/driver. The device is functionally equivalent to the EP16 and LVEP16 devices but with high gain output. QHG and QHG outputs have a DC gain several times larger than the DC gain of an EP16. The VBB pin, an internally generated volt

ONSEMI

安森美半导体

3.3V / 5VECL Differential Receiver/Driver with High Gain

Description The EP16VA is a world−class differential receiver/driver. The device is functionally equivalent to the EP16 and LVEP16 devices but with high gain output. QHG and QHG outputs have a DC gain several times larger than the DC gain of an EP16. The VBB pin, an internally generated volt

ONSEMI

安森美半导体

3.3V / 5VECL Differential Receiver/Driver with High Gain

Description The EP16VA is a world−class differential receiver/driver. The device is functionally equivalent to the EP16 and LVEP16 devices but with high gain output. QHG and QHG outputs have a DC gain several times larger than the DC gain of an EP16. The VBB pin, an internally generated volt

ONSEMI

安森美半导体

3.3V / 5V ECL Quad Differential Driver/Receiver

3.3V / 5V ECL Quad Differential Driver/Receiver Description The MC10/100EP17 is a 4-bit differential line receiver based on the EP17 device. The >3.0 GHz maximum frequency provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The VBB pin, an

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3.3V / 5V ECL Quad Differential Driver/Receiver

3.3V / 5V ECL Quad Differential Driver/Receiver Description The MC10/100EP17 is a 4-bit differential line receiver based on the EP17 device. The >3.0 GHz maximum frequency provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The VBB pin, an

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安森美半导体

3.3V / 5V ECL Quad Differential Driver/Receiver

3.3V / 5V ECL Quad Differential Driver/Receiver Description The MC10/100EP17 is a 4-bit differential line receiver based on the EP17 device. The >3.0 GHz maximum frequency provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The VBB pin, an

ONSEMI

安森美半导体

3.3V / 5V ECL Quad Differential Driver/Receiver

3.3V / 5V ECL Quad Differential Driver/Receiver Description The MC10/100EP17 is a 4-bit differential line receiver based on the EP17 device. The >3.0 GHz maximum frequency provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The VBB pin, an

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3.3V ECL Programmable Delay Chip

The MC10/100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The 100 Series contains temperature compensation. • Maximum Input Clock Frequency >1.2 GHz Typical • Progra

ONSEMI

安森美半导体

Clock Management Design Using Low Skew and Low Jitter Devices

Why Do We Need Clock Management? Can you imagine the chaos in our world if our clocks or watches were not synchronized to Greenwich Mean Time? How would trains, buses, and airplanes run on schedule? The miniseries Longitude was the story of a man who made a major technological breakthrough by inv

ONSEMI

安森美半导体

3.3V ECL Programmable Delay Chip

The MC10/100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The 100 Series contains temperature compensation. • Maximum Input Clock Frequency >1.2 GHz Typical • Progra

ONSEMI

安森美半导体

3.3V ECL Programmable Delay Chip

The MC10/100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The 100 Series contains temperature compensation. • Maximum Input Clock Frequency >1.2 GHz Typical • Progra

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安森美半导体

MC100EP产品属性

  • 类型

    描述

  • 型号

    MC100EP

  • 制造商

    ONSEMI

  • 制造商全称

    ON Semiconductor

  • 功能描述

    3.3V/5V ECL 4−Input OR/NOR

更新时间:2025-12-25 19:00:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
ON
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SOP
20000
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SMD
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