The MC10/100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition.

The 100 Series contains temperature compensation.

• Maximum Input Clock Frequency >1.2 GHz Typical

• Programmable Range: 0 ns to 10 ns

• Delay Range: 2.2 ns to 12.2 ns

• 10 ps Increments

• PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V

• NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.6 V

• Open Input Default State

• Safety Clamp on Inputs

• A Logic High on the EN Pin Will Force Q to Logic Low

• D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL Inputs

• VBB Output Reference Voltage

• Pb−Free Packages are Available