MC100EP1价格
参考价格:¥69.5122
型号:MC100EP101FAG 品牌:ON Semiconductor 备注:这里有MC100EP1多少钱,2026年最近7天走势,今日出价,今日竞价,MC100EP1批发/采购报价,MC100EP1行情走势销售排行榜,MC100EP1报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
MC100EP1 | 3.3V / 5V ECL Quad 2-Input Differential AND/NAND Description The MC10/100EP105 is a quad 2−input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP105 is ideal for applications requiring the fastest AC performance available. The 100 Ser | ONSEMI 安森美半导体 | ||
3.3V / 5V ECL Quad 2-Input Differential AND/NAND Description The MC10/100EP105 is a quad 2−input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP105 is ideal for applications requiring the fastest AC performance available. The 100 Ser | ONSEMI 安森美半导体 | |||
ECL Quad 2-Input Differential AND/NAND Gate The MC10/100EP105 is a quad 2-input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP105 is ideal for applications requiring the fastest AC performance available.The 100 Series contains temp • 275ps Typical Propagation Delay\n• Maximum Frequency > 3 Ghz Typical\n• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V\n• NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V\n• Open Input Default State\n• Safety Clamp on Inputs\n• Pb-Free Packages are Available; | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Quad 2-Input Differential AND/NAND Description The MC10/100EP105 is a quad 2−input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP105 is ideal for applications requiring the fastest AC performance available. The 100 Ser | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Quad 2-Input Differential AND/NAND Description The MC10/100EP105 is a quad 2−input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP105 is ideal for applications requiring the fastest AC performance available. The 100 Ser | ONSEMI 安森美半导体 | |||
Clock / Data Fanout Buffer, 1:2 Differential, ECL, 3.3 V / 5.0 V The MC10EP11 is a differential 1 to 2 fanout buffer. The device is pin and functionally equivalent to the LVEL11 device. With AC performance much faster than the LVEL11 device, the EP11 is ideal for applications requiring the fastest AC performance available. • 220 ps Typical Propagation Delay\n• Maximum Frequency > 3 GHz Typical\n• PECL Mode Operating Range: VCC= 3.0 V to 5.5 V with VEE= 0 V\n• NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -5.5 V\n• Open Input Default State\n• Safety Clamp on Inputs\n• Q Outputs Will Default LOW with Inputs Op; | ONSEMI 安森美半导体 | |||
Differential Line Receiver / Driver The MC10EP116/100EP116 is a 6-bit differential line receiver based on the EP16 device. The 3.0GHz bandwidth provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The VBB pin, an internally generated voltage supply, is available to this device onl • 260 ps Typical Propagation Delay\n• Maximum Frequency > 3 GHz Typical\n• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V\n• NECL Mode Operating Range: VCC = 0 V with VEE =-3.0 V to -5.5 V\n• Open Input Default State\n• Safety Clamp on Inputs\n• Q Output will default LOW with inputs ; | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock Description The MC10/100EP131 is a Quad Master−slaved D flip−flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables. With AC performance faster than the E131 device, the EP131 is ideal for applications requiring | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock Description The MC10/100EP131 is a Quad Master−slaved D flip−flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables. With AC performance faster than the E131 device, the EP131 is ideal for applications requiring | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Quad D Flip-Flop with Set, Reset, and Differential Clock Description The MC10/100EP131 is a Quad Master−slaved D flip−flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables. With AC performance faster than the E131 device, the EP131 is ideal for applications requiring | ONSEMI 安森美半导体 | |||
첨2/4, 첨4./5/6 Clock Generation Chip Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a di | ONSEMI 安森美半导体 | |||
Clock Management Design Using Low Skew and Low Jitter Devices Why Do We Need Clock Management? Can you imagine the chaos in our world if our clocks or watches were not synchronized to Greenwich Mean Time? How would trains, buses, and airplanes run on schedule? The miniseries Longitude was the story of a man who made a major technological breakthrough by inv | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL /2/4, /4/5/6 Clock Generation Chip Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a di | ONSEMI 安森美半导体 | |||
첨2/4, 첨4./5/6 Clock Generation Chip Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a di | ONSEMI 安森美半导体 | |||
첨2/4, 첨4./5/6 Clock Generation Chip Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a di | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL /2/4, /4/5/6 Clock Generation Chip Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a di | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL /2/4, /4/5/6 Clock Generation Chip Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a di | ONSEMI 安森美半导体 | |||
첨2/4, 첨4./5/6 Clock Generation Chip Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a di | ONSEMI 安森美半导体 | |||
첨2/4, 첨4./5/6 Clock Generation Chip Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a di | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL /2/4, /4/5/6 Clock Generation Chip Description The MC10/100EP139 is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a di | ONSEMI 安森美半导体 | |||
3.3 V / 5 V ECL 9-Bit Shift Register 3.3 V / 5 V ECL 9−Bit Shift Register The MC10EP/100EP142 is a 9−bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in only one direction. The nine inputs D0 − D8 accept parallel | ONSEMI 安森美半导体 | |||
3.3 V / 5 V ECL 9-Bit Shift Register 3.3 V / 5 V ECL 9−Bit Shift Register The MC10EP/100EP142 is a 9−bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in only one direction. The nine inputs D0 − D8 accept parallel | ONSEMI 安森美半导体 | |||
3.3 V / 5 V ECL 9-Bit Shift Register 3.3 V / 5 V ECL 9−Bit Shift Register The MC10EP/100EP142 is a 9−bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in only one direction. The nine inputs D0 − D8 accept parallel | ONSEMI 安森美半导体 | |||
3.3 V / 5 V ECL 9-Bit Shift Register 3.3 V / 5 V ECL 9−Bit Shift Register The MC10EP/100EP142 is a 9−bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in only one direction. The nine inputs D0 − D8 accept parallel | ONSEMI 安森美半导体 | |||
3.3 V / 5 V ECL 9-Bit Shift Register 3.3 V / 5 V ECL 9−Bit Shift Register The MC10EP/100EP142 is a 9−bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in only one direction. The nine inputs D0 − D8 accept parallel | ONSEMI 安森美半导体 | |||
3.3 V / 5 V ECL 9-Bit Shift Register 3.3 V / 5 V ECL 9−Bit Shift Register The MC10EP/100EP142 is a 9−bit shift register, designed with byte-parity applications in mind. The MC10/100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in only one direction. The nine inputs D0 − D8 accept parallel | ONSEMI 安森美半导体 | |||
Clock Management Design Using Low Skew and Low Jitter Devices Why Do We Need Clock Management? Can you imagine the chaos in our world if our clocks or watches were not synchronized to Greenwich Mean Time? How would trains, buses, and airplanes run on schedule? The miniseries Longitude was the story of a man who made a major technological breakthrough by inv | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Differential Receiver/Driver with Internal Termination Description The EP16T is a world−class differential receiver/driver. The device is functionally equivalent to the EP16 with internal termination resistors. A 50 resistor is connected from the D input to the VT pin and from the D input to the VT pin. Tie the VT and VT pins to VTT supply (VCC − | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Differential Receiver/Driver with Internal Termination Description The EP16T is a world−class differential receiver/driver. The device is functionally equivalent to the EP16 with internal termination resistors. A 50 resistor is connected from the D input to the VT pin and from the D input to the VT pin. Tie the VT and VT pins to VTT supply (VCC − | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Differential Receiver/Driver with Internal Termination Description The EP16T is a world−class differential receiver/driver. The device is functionally equivalent to the EP16 with internal termination resistors. A 50 resistor is connected from the D input to the VT pin and from the D input to the VT pin. Tie the VT and VT pins to VTT supply (VCC − | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Differential Receiver/Driver with Internal Termination Description The EP16T is a world−class differential receiver/driver. The device is functionally equivalent to the EP16 with internal termination resistors. A 50 resistor is connected from the D input to the VT pin and from the D input to the VT pin. Tie the VT and VT pins to VTT supply (VCC − | ONSEMI 安森美半导体 | |||
3.3V / 5VECL Differential Receiver/Driver with High Gain Description The EP16VA is a world−class differential receiver/driver. The device is functionally equivalent to the EP16 and LVEP16 devices but with high gain output. QHG and QHG outputs have a DC gain several times larger than the DC gain of an EP16. The VBB pin, an internally generated volt | ONSEMI 安森美半导体 | |||
3.3V / 5VECL Differential Receiver/Driver with High Gain Description The EP16VA is a world−class differential receiver/driver. The device is functionally equivalent to the EP16 and LVEP16 devices but with high gain output. QHG and QHG outputs have a DC gain several times larger than the DC gain of an EP16. The VBB pin, an internally generated volt | ONSEMI 安森美半导体 | |||
3.3V / 5VECL Differential Receiver/Driver with High Gain Description The EP16VA is a world−class differential receiver/driver. The device is functionally equivalent to the EP16 and LVEP16 devices but with high gain output. QHG and QHG outputs have a DC gain several times larger than the DC gain of an EP16. The VBB pin, an internally generated volt | ONSEMI 安森美半导体 | |||
3.3V / 5VECL Differential Receiver/Driver with High Gain Description The EP16VA is a world−class differential receiver/driver. The device is functionally equivalent to the EP16 and LVEP16 devices but with high gain output. QHG and QHG outputs have a DC gain several times larger than the DC gain of an EP16. The VBB pin, an internally generated volt | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Quad Differential Driver/Receiver 3.3V / 5V ECL Quad Differential Driver/Receiver Description The MC10/100EP17 is a 4-bit differential line receiver based on the EP17 device. The >3.0 GHz maximum frequency provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The VBB pin, an | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Quad Differential Driver/Receiver 3.3V / 5V ECL Quad Differential Driver/Receiver Description The MC10/100EP17 is a 4-bit differential line receiver based on the EP17 device. The >3.0 GHz maximum frequency provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The VBB pin, an | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Quad Differential Driver/Receiver 3.3V / 5V ECL Quad Differential Driver/Receiver Description The MC10/100EP17 is a 4-bit differential line receiver based on the EP17 device. The >3.0 GHz maximum frequency provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The VBB pin, an | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Quad Differential Driver/Receiver 3.3V / 5V ECL Quad Differential Driver/Receiver Description The MC10/100EP17 is a 4-bit differential line receiver based on the EP17 device. The >3.0 GHz maximum frequency provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators. The VBB pin, an | ONSEMI 安森美半导体 | |||
3.3V ECL Programmable Delay Chip The MC10/100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The 100 Series contains temperature compensation. • Maximum Input Clock Frequency >1.2 GHz Typical • Progra | ONSEMI 安森美半导体 | |||
Clock Management Design Using Low Skew and Low Jitter Devices Why Do We Need Clock Management? Can you imagine the chaos in our world if our clocks or watches were not synchronized to Greenwich Mean Time? How would trains, buses, and airplanes run on schedule? The miniseries Longitude was the story of a man who made a major technological breakthrough by inv | ONSEMI 安森美半导体 | |||
3.3V ECL Programmable Delay Chip The MC10/100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The 100 Series contains temperature compensation. • Maximum Input Clock Frequency >1.2 GHz Typical • Progra | ONSEMI 安森美半导体 | |||
3.3V ECL Programmable Delay Chip The MC10/100EP195 is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The 100 Series contains temperature compensation. • Maximum Input Clock Frequency >1.2 GHz Typical • Progra | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Quad 4?묲nput OR/NOR 文件:154.85 Kbytes Page:9 Pages | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Quad 4?묲nput OR/NOR 文件:154.85 Kbytes Page:9 Pages | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Quad 4?묲nput OR/NOR 文件:154.85 Kbytes Page:9 Pages | ONSEMI 安森美半导体 | |||
封装/外壳:32-LQFP 包装:卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带 描述:IC GATE OR/NOR QUAD 4INP 32LQFP 集成电路(IC) 门和反相器 - 多功能,可配置 | ONSEMI 安森美半导体 | |||
封装/外壳:32-LQFP 包装:卷带(TR)剪切带(CT)Digi-Reel® 得捷定制卷带 描述:IC GATE OR/NOR QUAD 4INP 32LQFP 集成电路(IC) 门和反相器 - 多功能,可配置 | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Quad 4?묲nput OR/NOR 文件:154.85 Kbytes Page:9 Pages | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Quad 4?묲nput OR/NOR 文件:154.85 Kbytes Page:9 Pages | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Quad 4?묲nput OR/NOR 文件:154.85 Kbytes Page:9 Pages | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Quad 4?묲nput OR/NOR 文件:154.85 Kbytes Page:9 Pages | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Quad 2?묲nput Differential AND/NAND 文件:160.73 Kbytes Page:11 Pages | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Quad 2?묲nput Differential AND/NAND 文件:160.73 Kbytes Page:11 Pages | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Quad 2?묲nput Differential AND/NAND 文件:160.73 Kbytes Page:11 Pages | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Quad 2?묲nput Differential AND/NAND 文件:160.73 Kbytes Page:11 Pages | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Quad 2?묲nput Differential AND/NAND 文件:160.73 Kbytes Page:11 Pages | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Quad 2?묲nput Differential AND/NAND 文件:160.73 Kbytes Page:11 Pages | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL Quad 2?묲nput Differential AND/NAND 文件:160.73 Kbytes Page:11 Pages | ONSEMI 安森美半导体 | |||
3.3V / 5V ECL 1:2 Differential Fanout Buffer 文件:163.89 Kbytes Page:11 Pages | ONSEMI 安森美半导体 |
MC100EP1产品属性
- 类型
描述
- Pb-free:
Pb
- Halide free:
H
- Status:
Active
- Type:
OR/NOR
- Channels:
4
- Input Level:
CML
- Output Level:
ECL
- VCC Typ (V):
3.3
- fToggle Max (MHz):
3000
- tpd Typ (ns):
0.3
- tJitter Typ (ps):
0.2
- tR & tF Max (ps):
200
- Package Type:
LQFP-32
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
ON |
2016+ |
SOP8 |
4000 |
只做原装,假一罚十,公司可开17%增值税发票! |
|||
ON(安森美) |
2511 |
TSSOP-20 |
5285 |
电子元器件采购降本 30%!公司原厂直采,砍掉中间差价 |
|||
PHOENIX/德国菲尼克斯 |
23+ |
NA |
5000 |
公司只做原装,可配单 |
|||
ON(安森美) |
24+ |
标准封装 |
8203 |
全新原装正品/价格优惠/质量保障 |
|||
PHOENIX |
23+ |
Connector |
13000 |
原厂授权一级代理,专业海外优势订货,价格优势、品种 |
|||
菲尼克斯连接器 |
247825 |
一级代理 原装正品 假一罚十 实单带接受价来谈 只 |
|||||
ON/安森美 |
2025+ |
QFP32 |
4480 |
原装进口价格优 请找坤融电子! |
|||
PHOENIXCONTACT |
2447 |
NA |
100500 |
一级代理专营品牌!原装正品,优势现货,长期排单到货 |
|||
5/2-ST-3 |
25+ |
1000 |
5000 |
百分百原装正品 真实公司现货库存 本公司只做原装 可 |
|||
ON(安森美) |
23+ |
- |
14826 |
公司只做原装正品,假一赔十 |
MC100EP1规格书下载地址
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CML / LVDS / LVPECL到LVCMOS / LVTTL转换-电压电平,CML / LVPECL / PECL到LVDS转换-电压电平,1 ns转换-电压电平,TSSOP-8 + 125 C转换-电压电平,VQFN-20 SMD / SMT转换-电压电平,SMD / SMT转换-电压电平
2020-7-28
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