HEX D-TYPE FLIP FLOP WITH CLEAR

DESCRIPTION The M54/74HCT174 is a high speed CMOS HEX DTYPEFLIP-FLOP WITH CLEAR fabricated in silicon gateC2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. ■ HIGH SPEED fMAX = 56 MHz (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION

HEX D-TYPE FLIP FLOP WITH CLEAR

DESCRIPTION The M74HCT174 is an high speed CMOS HEX D-TYPE FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology. Information signals applied to D inputs are transferred to the Q output on the positive going edge of the CLOCK (CK) pulse. When the CLEAR (CLR) input is held low, the Q

HEX D-TYPE FLIP FLOP WITH CLEAR

HEX D-TYPE FLIP FLOP WITH CLEAR

DESCRIPTION The M54/74HCT174 is a high speed CMOS HEX DTYPEFLIP-FLOP WITH CLEAR fabricated in silicon gateC2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. ■ HIGH SPEED fMAX = 56 MHz (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION

HEX D-TYPE FLIP FLOP WITH CLEAR

DESCRIPTION The M74HCT174 is an high speed CMOS HEX D-TYPE FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology. Information signals applied to D inputs are transferred to the Q output on the positive going edge of the CLOCK (CK) pulse. When the CLEAR (CLR) input is held low, the Q

HEX D-TYPE FLIP FLOP WITH CLEAR

DESCRIPTION The M54/74HCT174 is a high speed CMOS HEX DTYPEFLIP-FLOP WITH CLEAR fabricated in silicon gateC2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. ■ HIGH SPEED fMAX = 56 MHz (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION

HEX D-TYPE FLIP FLOP WITH CLEAR

DESCRIPTION The M54/74HCT174 is a high speed CMOS HEX DTYPEFLIP-FLOP WITH CLEAR fabricated in silicon gateC2MOS technology. It has the same high speed performance of LSTTL combined with true CMOS low power consumption. ■ HIGH SPEED fMAX = 56 MHz (TYP.) AT VCC = 5 V ■ LOW POWER DISSIPATION

HEX D-TYPE FLIP FLOP WITH CLEAR

DESCRIPTION The M74HCT174 is an high speed CMOS HEX D-TYPE FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology. Information signals applied to D inputs are transferred to the Q output on the positive going edge of the CLOCK (CK) pulse. When the CLEAR (CLR) input is held low, the Q

HEX D-TYPE FLIP FLOP WITH CLEAR

DESCRIPTION The M74HCT174 is an high speed CMOS HEX D-TYPE FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology. Information signals applied to D inputs are transferred to the Q output on the positive going edge of the CLOCK (CK) pulse. When the CLEAR (CLR) input is held low, the Q

HEX D-TYPE FLIP FLOP WITH CLEAR

DESCRIPTION The M74HCT174 is an high speed CMOS HEX D-TYPE FLIP FLOP WITH CLEAR fabricated with silicon gate C2MOS technology. Information signals applied to D inputs are transferred to the Q output on the positive going edge of the CLOCK (CK) pulse. When the CLEAR (CLR) input is held low, the Q

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：主复位 包装：卷带（TR） 描述：IC FF D-TYPE SNGL 6BIT 16SOP 集成电路（IC） 触发器

封装/外壳：16-TSSOP（0.173"，4.40mm 宽） 功能：主复位 包装：卷带（TR） 描述：IC FF D-TYPE SNGL 6BIT 16TSSOP 集成电路（IC） 触发器

Hex D-type flip-flop with reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT174 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Six edge-triggered D-type flip-flops • Asynchronous master reset • Output cap

Hex D-type flip-flop with reset; positive-edge trigger

1. General description The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requ

Hex D-type flip-flop with reset; positive-edge trigger

1. General description The 74HC174; 74HCT174 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requ

Hex D-type flip-flop with reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT174 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Six edge-triggered D-type flip-flops • Asynchronous master reset • Output cap

Hex D-type flip-flop with reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT174 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Six edge-triggered D-type flip-flops • Asynchronous master reset • Output cap