Hex D-type flip-flop with reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT174 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Six edge-triggered D-type flip-flops • Asynchronous master reset • Output cap

Hex D-type flip-flop with reset; positive-edge trigger

The 74HC174; 74HCT174 are hex positive edge -triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR ) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIG • Input levels:• For 74HC174: CMOS level\n• For 74HCT174: TTL level\n\n• Six edge-triggered D-type flip-flops\n• Asynchronous master reset\n• Complies with JEDEC standard no. 7A\n• ESD protection:• HBM JESD22-A114F exceeds 2000 V\n• MM JESD22-A115-A exceeds 200 V.\n\n• Multiple package options\n• Sp;

封装/外壳：16-SSOP（0.209"，5.30mm 宽） 功能：主复位 包装：卷带（TR） 描述：IC FF D-TYPE SNGL 6BIT 16SSOP 集成电路（IC） 触发器

封装/外壳：16-SSOP（0.209"，5.30mm 宽） 功能：主复位 包装：卷带（TR） 描述：IC FF D-TYPE SNGL 6BIT 16SSOP 集成电路（IC） 触发器

Hex D-type flip-flop with reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT174 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Six edge-triggered D-type flip-flops • Asynchronous master reset • Output cap

Hex D-type flip-flop with reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT174 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Six edge-triggered D-type flip-flops • Asynchronous master reset • Output cap

Hex D-type flip-flop with reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT174 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Six edge-triggered D-type flip-flops • Asynchronous master reset • Output cap

Hex D Flip-Flop with Common Clock and Reset with LSTTL Compatible Inputs

Hex D Flip-Flop with Common Clock and Reset with LSTTL Compatible Inputs High–Performance Silicon–Gate CMOS The MC74HCT174A is identical in pinout to the LS174. This device may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. This device consists of si