QUAD S - R LATCH

DESCRIPTION The M74HC279 is an high speed CMOS QUAD S - R LATCH fabricated with silicon gate C2MOS technology. ■ HIGH SPEED: tPD = 13ns (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN.) ■ SYMMETRICAL O

QUAD S - R LATCH

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Quad. S-R Latches

Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated steady-state input conditions were established

Octal D-type Flip-Flops (with Clear)

Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated steady-state input conditions were established

Octal D-type Flip-Flops (with Clear)

Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated steady-state input conditions were established

Octal D-type Flip-Flops (with Clear)

Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated steady-state input conditions were established