QUAD S - R LATCH

DESCRIPTION The M74HC279 is an high speed CMOS QUAD S - R LATCH fabricated with silicon gate C2MOS technology. ■ HIGH SPEED: tPD = 13ns (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN.) ■ SYMMETRICAL O

QUAD S - R LATCH

QUAD S - R LATCH

文件：239.26 Kbytes Page：10 Pages

QUAD S - R LATCH

DESCRIPTION The M74HC279 is an high speed CMOS QUAD S - R LATCH fabricated with silicon gate C2MOS technology. ■ HIGH SPEED: tPD = 13ns (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN.) ■ SYMMETRICAL O

QUAD S - R LATCH

DESCRIPTION The M74HC279 is an high speed CMOS QUAD S - R LATCH fabricated with silicon gate C2MOS technology. ■ HIGH SPEED: tPD = 13ns (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN.) ■ SYMMETRICAL O

QUAD S - R LATCH

DESCRIPTION The M74HC279 is an high speed CMOS QUAD S - R LATCH fabricated with silicon gate C2MOS technology. ■ HIGH SPEED: tPD = 13ns (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN.) ■ SYMMETRICAL O

QUAD S - R LATCH

DESCRIPTION The M74HC279 is an high speed CMOS QUAD S - R LATCH fabricated with silicon gate C2MOS technology. ■ HIGH SPEED: tPD = 13ns (TYP.) at VCC = 6V ■ LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C ■ HIGH NOISE IMMUNITY: VNIH = VNIL = 28 VCC (MIN.) ■ SYMMETRICAL O

QUAD S - R LATCH

文件：239.26 Kbytes Page：10 Pages

QUAD S - R LATCH

文件：239.26 Kbytes Page：10 Pages

QUAD S - R LATCH

文件：239.26 Kbytes Page：10 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC LATCH QUAD S-R 16-SOIC 集成电路（IC） 锁存器

Quad. S-R Latches

Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated steady-state input conditions were established

Octal D-type Flip-Flops (with Clear)

Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated steady-state input conditions were established

Octal D-type Flip-Flops (with Clear)

Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated steady-state input conditions were established

Octal D-type Flip-Flops (with Clear)

Description The latch is ideally suited for use as temporary stage for binary information processing and input/output units. When either S or R is low, output is dependent on R input. When both inputs are high, Output is stored before the indicated steady-state input conditions were established