5120 x 8-BIT x 2 LINE MEMORY

DESCRIPTION The M66281FP is high speed line memory that uses high performance silicon gate CMOS process technology and adopts the FIFO (First In First Out) structure consisting of 5120 words x 8 bits x 2. Since memory is available to simultaneously output 1 line delay and 2 line delay data, the

5120 횞 8-Bit 횞 2 Line Memory

Description The M66281FP is high speed line memory that uses high performance silicon gate CMOS process technology and adopts the FIFO (First In First Out) structure consisting of 5120 words × 8 bits × 2. Since memory is available to simultaneously output 1 line delay and 2 line delay data, the

5120 × 8-Bit × 2 Line Memory

Base lead provided for conventional transistor biasing

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ELP 14/3,5/5 Core (Without Clamp Recess)

文件：71.89 Kbytes Page：2 Pages

Ferrites and accessories

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Ferrites and accessories

文件：248.56 Kbytes Page：8 Pages

Ferrites and accessories

文件：248.56 Kbytes Page：8 Pages