Description

The M66281FP is high speed line memory that uses high performance silicon gate CMOS process technology and adopts the FIFO (First In First Out) structure consisting of 5120 words × 8 bits × 2.

Since memory is available to simultaneously output 1 line delay and 2 line delay data, the M66281FP is optimal for the compensation of data of multiple lines.

Features

• Memory configuration: 5120 words × 8 bits × 2 (dynamic memory)

• High speed cycle: 25 ns (Min)

• High speed access: 18 ns (Max)

• Output hold: 3 ns (Min)

• Reading and writing operations can be completely carried out independently and asynchronously

• Variable length delay bit

• Input/output: TTL direct connection allowable

• Output: 3 states

• Q00 to Q07: 1 line delay

• Q10 to Q17: 2 line delay

Application

Digital copying machine, laser beam printer, high speed facsimile, etc.