LMK05318 Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

1 Features 1• One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

采用 BAW 技术的超低抖动、单通道网络同步器时钟

Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

文件：1.52689 Mbytes Page：75 Pages

Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

文件：2.64559 Mbytes Page：86 Pages

LMK05318B Ultra-Low Jitter Clock Generator

1 Features • One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

LMK05318B Ultra-Low Jitter Clock Generator

1 Features • One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

LMK05318B-Q1 Ultra-Low Jitter Network Synchronizer and Clock Generator With BAW VCO for Automotive and Industrial Applications

1 Features • AEC-Q100 qualified for automotive applications – Temperature grade 2: –40°C to 105°C • Ultra-low jitter BAW VCO based Ethernet clocks – 50fs typical RMS jitter at 312.5MHz – 60fs typical RMS jitter at 156.25MHz • One high-performance Digital Phase-Locked Loop (DPLL) paired with

丝印代码：LK05318B；LMK05318B Ultra-Low Jitter Clock Generator

1 Features • One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

丝印代码：LK05318B；LMK05318B Ultra-Low Jitter Clock Generator

1 Features • One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

LMK05318B Ultra-Low Jitter Clock Generator

1 Features • One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

丝印代码：LK05318B；LMK05318B Ultra-Low Jitter Clock Generator

1 Features • One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

丝印代码：LK05318B；LMK05318B Ultra-Low Jitter Clock Generator

1 Features • One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

LMK05318B Ultra-Low Jitter Clock Generator

1 Features • One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

丝印代码：LK05318B；LMK05318B Ultra-Low Jitter Clock Generator

1 Features • One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

丝印代码：LK05318B；LMK05318B Ultra-Low Jitter Clock Generator

1 Features • One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

LMK05318B Ultra-Low Jitter Clock Generator

1 Features • One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

丝印代码：K05318BQ1；LMK05318B-Q1 Ultra-Low Jitter Network Synchronizer and Clock Generator With BAW VCO for Automotive and Industrial Applications

1 Features • AEC-Q100 qualified for automotive applications – Temperature grade 2: –40°C to 105°C • Ultra-low jitter BAW VCO based Ethernet clocks – 50fs typical RMS jitter at 312.5MHz – 60fs typical RMS jitter at 156.25MHz • One high-performance Digital Phase-Locked Loop (DPLL) paired with

丝印代码：K05318BQ1；LMK05318B-Q1 Ultra-Low Jitter Network Synchronizer and Clock Generator With BAW VCO for Automotive and Industrial Applications

1 Features • AEC-Q100 qualified for automotive applications – Temperature grade 2: –40°C to 105°C • Ultra-low jitter BAW VCO based Ethernet clocks – 50fs typical RMS jitter at 312.5MHz – 60fs typical RMS jitter at 156.25MHz • One high-performance Digital Phase-Locked Loop (DPLL) paired with

丝印代码：K05318A32500；LMK05318 Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

1 Features 1• One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

丝印代码：K05318A32500；LMK05318 Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

1 Features 1• One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

LMK05318 Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

1 Features 1• One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

丝印代码：K05318A32500；LMK05318 Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

1 Features 1• One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

丝印代码：K05318A32500；LMK05318 Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

1 Features 1• One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

LMK05318 Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

1 Features 1• One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

丝印代码：K05318A32500；LMK05318 Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

1 Features 1• One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

丝印代码：K05318A32500；LMK05318 Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

1 Features 1• One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

LMK05318 Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

1 Features 1• One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

文件：2.64559 Mbytes Page：86 Pages

采用 BAW 技术的超低抖动、单通道网络同步器时钟

LMK05318B Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

文件：3.51182 Mbytes Page：87 Pages

Automotive ultra-low jitter network synchronizer and clock generator

封装/外壳：48-VFQFN 裸露焊盘 包装：托盘 描述：IC POWER 集成电路（IC） 时钟发生器，PLL，频率合成器

丝印代码：LK05318B；LMK05318B Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

文件：3.51182 Mbytes Page：87 Pages

丝印代码：LK05318B；LMK05318B Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

文件：3.51182 Mbytes Page：87 Pages

封装/外壳：48-VFQFN 裸露焊盘 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：ULTRA-LOW JITTER SINGLE CHANNEL 集成电路（IC） 时钟发生器，PLL，频率合成器

丝印代码：K05318A32500；Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

文件：2.64559 Mbytes Page：86 Pages

丝印代码：K05318A32500；Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

文件：2.64559 Mbytes Page：86 Pages

Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

文件：1.52689 Mbytes Page：75 Pages