LMK05318 Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

1 Features 1• One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

文件：2.64559 Mbytes Page：86 Pages

封装/外壳：48-VFQFN 裸露焊盘 包装：卷带（TR） 描述：IC CLOCK BUFFER 集成电路（IC） 时钟发生器，PLL，频率合成器

LMK05318 Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

1 Features 1• One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

文件：1.52689 Mbytes Page：75 Pages

Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

文件：2.64559 Mbytes Page：86 Pages

LMK05318 Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

1 Features 1• One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

LMK05318 Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

1 Features 1• One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

LMK05318 Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

1 Features 1• One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

LMK05318 Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

1 Features 1• One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

LMK05318 Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

1 Features 1• One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

LMK05318B Ultra-Low Jitter Clock Generator

1 Features • One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs) With Industry-Leading Jitter

LMK05318B Ultra-Low Jitter Network Synchronizer Clock With Two Frequency Domains

文件：3.51182 Mbytes Page：87 Pages