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ISPLSI1032价格
参考价格：￥211.2081
型号：ISPLSI1032-60LT 品牌： 备注：这里有ISPLSI1032多少钱，2026年最近7天走势，今日出价，今日竞价，ISPLSI1032批发/采购报价，ISPLSI1032行情走势销售排行榜，ISPLSI1032报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
ISPLSI1032 | In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 |   | |
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI 1032/883 is a High-Density Programmable Logic Device processed in full compliance to MIL-STD-883. This military grade device contains 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP p | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI 1032/883 is a High-Density Programmable Logic Device processed in full compliance to MIL-STD-883. This military grade device contains 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP p | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | LATTICE 莱迪思 | | ||
High-Density Programmable Logic Description\nThe ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. • HIGH DENSITY PROGRAMMABLE LOGIC\n — 6000 PLD Gates\n — 64 I/O Pins, Eight Dedicated Inputs\n — 192 Registers\n — High Speed Global Interconnect\n — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.\n — Small Logic Block Size for Random Logic\n• HIGH PERFORMANC; | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements | LATTICE 莱迪思 | | ||
High-Density Programmable Logic Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements | LATTICE 莱迪思 | | ||
High-Density Programmable Logic Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements | LATTICE 莱迪思 | | ||
High-Density Programmable Logic Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements | LATTICE 莱迪思 | | ||
High-Density Programmable Logic Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements | LATTICE 莱迪思 | | ||
High-Density Programmable Logic Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements | LATTICE 莱迪思 | | ||
High-Density Programmable Logic Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements | LATTICE 莱迪思 | | ||
High-Density Programmable Logic Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements | LATTICE 莱迪思 | | ||
High-Density Programmable Logic Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements | LATTICE 莱迪思 | | ||
High-Density Programmable Logic Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements | LATTICE 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements | LATTICE 莱迪思 | |
ISPLSI1032产品属性
- 类型
描述
- 型号
ISPLSI1032
- 制造商
LATTICE
- 制造商全称
Lattice Semiconductor
- 功能描述
In-System Programmable High Density PLD
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
Lattice(莱迪斯) |
24+ |
标准封装 |
7268 |
原厂渠道供应,大量现货,原型号开票。 |
|||
LATTICE/莱迪斯 |
26+ |
TQFP |
9880 |
只做原装,欢迎来电资询 |
|||
LATTICE/莱迪斯 |
25+ |
QFP |
12496 |
LATTICE/莱迪斯原装正品ISPLSI1032E-100LT即刻询购立享优惠#长期有货 |
|||
LATTICE |
24+ |
PLCC |
8500 |
只做原装正品假一赔十为客户做到零风险!! |
|||
LATTICE/莱迪斯 |
97+ |
QFP |
50 |
原装现货,大量需求可以排单 |
|||
LATTICE |
25+ |
5282 |
公司原装现货常备库存! |
||||
LATTICE |
2025+ |
PLCC |
3783 |
全新原装、公司现货热卖 |
|||
LATTICE/莱迪斯 |
25+ |
PLCC84 |
12500 |
全新原装现货,假一赔十 |
|||
LATTICE/莱迪斯 |
0014+ |
明嘉莱只做原装正品现货 |
2510000 |
TQFP-100 |
|||
Lattice(莱迪斯) |
25+ |
N/A |
8577 |
原装正品现货,原厂订货,可支持含税原型号开票。 |
ISPLSI1032芯片相关品牌
ISPLSI1032规格书下载地址
ISPLSI1032参数引脚图相关
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- l101
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- jumper
- jtag接口
- jk触发器
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- IS-T-F
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- ISPLSI1048EA-100LQ128
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- ISPLSI1048E-50LQI
- ISPLSI1048E-100LQN
- ISPLSI1048E-10>
- ISPLSI1032E-70LTNI
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- ISPLSI1032E-70LJNI
- ISPLSI1032E-125LTN
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- ISPLSI1032-60LT
- ISPLSI1016E-80LTN44I
- ISPLSI1016E-80LTN44
- ISPLSI1016E-80LT44
- ISPLSI1016E-80LJNI
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- ISPGDX80VA-7TN100
- ISPGDX2
- ISPGDX160VA-7B208
- ISPGDX160VA-3B208
- ISPGDX
- ISPD65
- ISPD64
- ISPD63
- ISPD62
- ISPD61
- ISPD60
- ISPC.91A.09.0092E
- ISPC.86A.09.0092E
- ISPB40
- ISPB35
- ISPB20
- ISPA60
- ISPA40
- ISPA20
- ISPA06
- ISP847X
- ISP847
- ISP845X
- ISP845
- ISP817X
- ISP817CXSMT/R
- ISP817CXSM
- ISP817C
- ISP817AXG
- ISP815SMTR
- ISP815
ISPLSI1032数据表相关新闻
ISPLSI1032-60LG/883
制造商: Lattice 产品种类: CPLD - 复杂可编程逻辑器件 产品: ispLSI 1032 大电池数量: 128 逻辑数组块数量——LAB: 32 最大工作频率: 83 MHz 传播延迟—最大值: 20 ns 输入/输出端数量: 64 I/O 工作电源电压: 5 V 最小工作温度: - 55 C 最大工作温度: + 125 C 封装 / 箱体: CPGA-84 高度: 3.68 mm
2019-12-18ISPLSI1032E-70LJN，lattice专业户，现货支持
德信电子（香港）有限公司 客服经理：林先生 联系电话：0755-33359577
2019-7-22ISPLSI1016E-100LT44，lattice专业户，现货支持
德信电子（香港）有限公司 客服经理：林先生 联系电话：0755-33359577
2019-7-22ISPLSI1016-60LJ，lattice专业户，现货支持
德信电子（香港）有限公司 客服经理：林先生 联系电话：0755-33359577
2019-7-22ISPLSI1032E-125LTN，lattice专业户，现货支持
德信电子（香港）有限公司 客服经理：林先生 联系电话：0755-33359577
2019-7-22ISPLSI1016E-80LJN，lattice专业户，现货支持
德信电子（香港）有限公司 客服经理：林先生 联系电话：0755-33359577
2019-7-22
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