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ISPLSI1032价格

参考价格：￥211.2081

型号：ISPLSI1032-60LT 品牌：备注：这里有ISPLSI1032多少钱，2025年最近7天走势，今日出价，今日竞价，ISPLSI1032批发/采购报价，ISPLSI1032行情走势销售排行榜，ISPLSI1032报价。

型号	功能描述	生产厂家企业	LOGO
ISPLSI1032	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-60	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-60LG	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-60LG/833	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-60LG/883	In-System Programmable High Density PLD Description The ispLSI 1032/883 is a High-Density Programmable Logic Device processed in full compliance to MIL-STD-883. This military grade device contains 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP p	Lattice 莱迪思	Lattice
ISPLSI1032-60LGI	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-60LGSLASH833	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-60LGSLASH883	In-System Programmable High Density PLD Description The ispLSI 1032/883 is a High-Density Programmable Logic Device processed in full compliance to MIL-STD-883. This military grade device contains 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP p	Lattice 莱迪思	Lattice
ISPLSI1032-60LJ	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-60LJ/833	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-60LJI	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-60LJSLASH833	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-60LT	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-60LT/833	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-60LTI	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-60LTSLASH833	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-80	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-80LG	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-80LG/833	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-80LGI	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-80LGSLASH833	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-80LJ	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-80LJ/833	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-80LJI	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-80LJSLASH833	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-80LT	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-80LT/833	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-80LTI	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-80LTSLASH833	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-90	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-90LG	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-90LG/833	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-90LGI	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-90LGSLASH833	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-90LJ	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-90LJ/833	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-90LJI	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-90LJSLASH833	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-90LT	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-90LT/833	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-90LTI	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032-90LTSLASH833	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.	Lattice 莱迪思	Lattice
ISPLSI1032E-100LJ	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements	Lattice 莱迪思	Lattice
ISPLSI1032E-100LJ	High-Density Programmable Logic Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements	Lattice 莱迪思	Lattice
ISPLSI1032E-100LT	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements	Lattice 莱迪思	Lattice
ISPLSI1032E-100LT	High-Density Programmable Logic Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements	Lattice 莱迪思	Lattice
ISPLSI1032E-125LJ	High-Density Programmable Logic Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements	Lattice 莱迪思	Lattice
ISPLSI1032E-125LJ	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements	Lattice 莱迪思	Lattice
ISPLSI1032E-125LT	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements	Lattice 莱迪思	Lattice
ISPLSI1032E-125LT	High-Density Programmable Logic Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements	Lattice 莱迪思	Lattice
ISPLSI1032E-70LJ	High-Density Programmable Logic Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements	Lattice 莱迪思	Lattice
ISPLSI1032E-70LJ	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements	Lattice 莱迪思	Lattice
ISPLSI1032E-70LJI	High-Density Programmable Logic Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements	Lattice 莱迪思	Lattice
ISPLSI1032E-70LT	High-Density Programmable Logic Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements	Lattice 莱迪思	Lattice
ISPLSI1032E-70LT	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements	Lattice 莱迪思	Lattice
ISPLSI1032E-70LTI	High-Density Programmable Logic Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements	Lattice 莱迪思	Lattice
ISPLSI1032E-80LJ	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements	Lattice 莱迪思	Lattice
ISPLSI1032E-80LJ	High-Density Programmable Logic Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements	Lattice 莱迪思	Lattice
ISPLSI1032E-80LT	High-Density Programmable Logic Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements	Lattice 莱迪思	Lattice
ISPLSI1032E-80LT	In-System Programmable High Density PLD Description The ispLSI and pLSI 1032E are High Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements	Lattice 莱迪思	Lattice

ISPLSI1032产品属性

类型
描述
型号
ISPLSI1032
制造商
LATTICE
制造商全称
Lattice Semiconductor
功能描述
In-System Programmable High Density PLD

ISPLSI1032供应商更多...

更新时间：2025-11-18 23:00:00

IC供应商	芯片型号	品牌	批号	封装	库存	备注	价格
深圳市高捷芯城科技有限公司	ISPLSI1032-60LT	Lattice(莱迪斯)	24+	标准封装	7268	原厂渠道供应,大量现货,原型号开票。	询价
中天科工半导体（深圳）有限公司	ISPLSI1032E-100LT	LATTICE/莱迪斯	25+	QFP	12496	LATTICE/莱迪斯原装正品ISPLSI1032E-100LT即刻询购立享优惠#长期有货	询价
深圳市科恒伟业电子有限公司	ISPLSI1032E-70LJN	LATTICE	24+	PLCC	8500	只做原装正品假一赔十为客户做到零风险!!	询价
深圳市凌旭科技有限公司	ISPLSI1032E-70LJI	LATTICE	21+	PLCC84	1697	十年信誉,只做原装,有挂就有现货!	询价
千层芯半导体(深圳)有限公司	ISPLSI1032-60LG/883	E2V	24+	SMD	500	“芯达集团”专营军工百分之百原装进口	询价
深圳诚思涵科技有限公司	ISPLSI1032E-100LT	LATTICE/莱迪斯	24+	TQFP100	8003	只做原装正品现货	询价
深圳市宏捷佳电子科技有限公司	ISPLSI1032E-70LTI	LATTICE	2023+	TQFP100	53500	正品,原装现货	询价
深圳市富芯乐电子科技有限公司	ISPLSI1032-60LG	LATTICE	24+	NA	2000	只做原装正品现货欢迎来电查询15919825718	询价
深圳市明嘉莱科技有限公司	ISPLSI1032E-100LT	LATTICE/莱迪斯	0014+	明嘉莱只做原装正品现货	2510000	TQFP-100	询价
深圳市得捷芯城科技有限公司	ISPLSI1032E-70LJ	Lattice(莱迪斯)	24+	N/A	7413	原厂可订货,技术支持,直接渠道。可签保供合同	询价

ISPLSI1032芯片相关品牌

ISPLSI1032规格书下载地址

ISPLSI1032参数引脚图相关

ISPLSI1032数据表相关新闻

ISPLSI1032-60LG/883
制造商: Lattice 产品种类: CPLD - 复杂可编程逻辑器件产品: ispLSI 1032 大电池数量: 128 逻辑数组块数量——LAB: 32 最大工作频率: 83 MHz 传播延迟—最大值: 20 ns 输入/输出端数量: 64 I/O 工作电源电压: 5 V 最小工作温度: - 55 C 最大工作温度: + 125 C 封装 / 箱体: CPGA-84 高度: 3.68 mm
2019-12-18
ISPLSI1032E-70LJN，lattice专业户，现货支持
德信电子（香港）有限公司客服经理：林先生联系电话：0755-33359577
2019-7-22
ISPLSI1016E-100LT44，lattice专业户，现货支持
德信电子（香港）有限公司客服经理：林先生联系电话：0755-33359577
2019-7-22
ISPLSI1016-60LJ，lattice专业户，现货支持
德信电子（香港）有限公司客服经理：林先生联系电话：0755-33359577
2019-7-22
ISPLSI1032E-125LTN，lattice专业户，现货支持
德信电子（香港）有限公司客服经理：林先生联系电话：0755-33359577
2019-7-22
ISPLSI1016E-80LJN，lattice专业户，现货支持
德信电子（香港）有限公司客服经理：林先生联系电话：0755-33359577
2019-7-22

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