型号 功能描述 生产厂家 企业 LOGO 操作
ISPLSI1032-90

In-System Programmable High Density PLD

Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.

Lattice

莱迪思

In-System Programmable High Density PLD

Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements.

Lattice

莱迪思

High-Density Programmable Logic

文件:256.36 Kbytes Page:19 Pages

Lattice

莱迪思

High-Density Programmable Logic

文件:256.36 Kbytes Page:19 Pages

Lattice

莱迪思

High-Density Programmable Logic

文件:256.36 Kbytes Page:19 Pages

Lattice

莱迪思

High-Density Programmable Logic

文件:256.36 Kbytes Page:19 Pages

Lattice

莱迪思

ISPLSI1032-90产品属性

  • 类型

    描述

  • 型号

    ISPLSI1032-90

  • 制造商

    LATTICE

  • 制造商全称

    Lattice Semiconductor

  • 功能描述

    In-System Programmable High Density PLD

更新时间:2025-10-5 23:00:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
Lattice(莱迪斯)
24+
标准封装
32048
原厂渠道供应,大量现货,原型号开票。
LATTE/莱迪斯
24+
NA/
4083
原装现货,当天可交货,原型号开票
LATTICE
24+
PLCC
80000
只做自己库存 全新原装进口正品假一赔百 可开13%增
LATTICE/莱迪斯
25+
QFP
996880
只做原装,欢迎来电资询
LATTICE/莱迪斯
2450+
QFP
6540
只做原装正品假一赔十为客户做到零风险!!
LATTICE
25+23+
PLCC84
24167
绝对原装正品全新进口深圳现货
Lattice
2000
115
公司优势库存 热卖中!!
LATTICE
原厂封装
9800
原装进口公司现货假一赔百
LATTICE
23+
SOIC8
5000
原装正品,假一罚十
LATTICE
24+
QFP
875

ISPLSI1032-90数据表相关新闻