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ISPLSI1032-60价格
参考价格：￥211.2081
型号：ISPLSI1032-60LT 品牌： 备注：这里有ISPLSI1032-60多少钱，2025年最近7天走势，今日出价，今日竞价，ISPLSI1032-60批发/采购报价，ISPLSI1032-60行情走势销售排行榜，ISPLSI1032-60报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
ISPLSI1032-60 | In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | Lattice 莱迪思 |   | |
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | Lattice 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | Lattice 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI 1032/883 is a High-Density Programmable Logic Device processed in full compliance to MIL-STD-883. This military grade device contains 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP p | Lattice 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | Lattice 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | Lattice 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI 1032/883 is a High-Density Programmable Logic Device processed in full compliance to MIL-STD-883. This military grade device contains 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP p | Lattice 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | Lattice 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | Lattice 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | Lattice 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | Lattice 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | Lattice 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | Lattice 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | Lattice 莱迪思 | | ||
In-System Programmable High Density PLD Description The ispLSI and pLSI 1032 are High-Density Programmable Logic Devices containing 192 Registers, 64 Universal I/O pins, eight Dedicated Input pins, four Dedicated Clock Input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. | Lattice 莱迪思 | | ||
In-System Programmable High Density PLD | Lattice 莱迪思 | | ||
High-Density Programmable Logic 文件：256.36 Kbytes Page：19 Pages | Lattice 莱迪思 | | ||
High-Density Programmable Logic 文件：256.36 Kbytes Page：19 Pages | Lattice 莱迪思 | | ||
High-Density Programmable Logic | Lattice 莱迪思 | | ||
High-Density Programmable Logic 文件：256.36 Kbytes Page：19 Pages | Lattice 莱迪思 | | ||
High-Density Programmable Logic 文件：256.36 Kbytes Page：19 Pages | Lattice 莱迪思 | | ||
High-Density Programmable Logic 文件：256.36 Kbytes Page：19 Pages | Lattice 莱迪思 | | ||
High-Density Programmable Logic 文件：256.36 Kbytes Page：19 Pages | Lattice 莱迪思 | | ||
High-Density Programmable Logic 文件：256.36 Kbytes Page：19 Pages | Lattice 莱迪思 | | ||
High-Density Programmable Logic 文件：256.36 Kbytes Page：19 Pages | Lattice 莱迪思 | | ||
High-Density Programmable Logic 文件：256.36 Kbytes Page：19 Pages | Lattice 莱迪思 | | ||
High-Density Programmable Logic 文件：256.36 Kbytes Page：19 Pages | Lattice 莱迪思 | |
ISPLSI1032-60产品属性
- 类型
描述
- 型号
ISPLSI1032-60
- 制造商
LATTICE
- 制造商全称
Lattice Semiconductor
- 功能描述
In-System Programmable High Density PLD
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
LATTICE |
2023+ |
SMD |
898 |
安罗世纪电子只做原装正品货 |
|||
LATTE/莱迪斯 |
24+ |
NA/ |
4420 |
原装现货,当天可交货,原型号开票 |
|||
Lattice(莱迪斯) |
24+ |
标准封装 |
7268 |
原厂渠道供应,大量现货,原型号开票。 |
|||
LATTICE |
24+ |
PLCC |
80000 |
只做自己库存 全新原装进口正品假一赔百 可开13%增 |
|||
xilinx |
22+ |
PLCC |
6800 |
||||
LATTICE/莱迪斯 |
25+ |
PLCC84 |
54658 |
百分百原装现货 实单必成 |
|||
LATTICE/莱迪斯 |
22+ |
PLCC84 |
100000 |
代理渠道/只做原装/可含税 |
|||
LATTICE |
13+ |
TQFP100 |
1170 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
|||
LATTICE/莱迪斯 |
2450+ |
PLCC |
8850 |
只做原装正品假一赔十为客户做到零风险!! |
|||
LATTICE |
25+ |
QFP |
4500 |
全新原装、诚信经营、公司现货销售 |
ISPLSI1032-60规格书下载地址
ISPLSI1032-60参数引脚图相关
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ISPLSI1032-60数据表相关新闻
ISPLSI1032-60LG/883
制造商: Lattice 产品种类: CPLD - 复杂可编程逻辑器件 产品: ispLSI 1032 大电池数量: 128 逻辑数组块数量——LAB: 32 最大工作频率: 83 MHz 传播延迟—最大值: 20 ns 输入/输出端数量: 64 I/O 工作电源电压: 5 V 最小工作温度: - 55 C 最大工作温度: + 125 C 封装 / 箱体: CPGA-84 高度: 3.68 mm
2019-12-18ISPLSI1032E-70LJN，lattice专业户，现货支持
德信电子（香港）有限公司 客服经理：林先生 联系电话：0755-33359577
2019-7-22ISPLSI1016E-100LT44，lattice专业户，现货支持
德信电子（香港）有限公司 客服经理：林先生 联系电话：0755-33359577
2019-7-22ISPLSI1016-60LJ，lattice专业户，现货支持
德信电子（香港）有限公司 客服经理：林先生 联系电话：0755-33359577
2019-7-22ISPLSI1032E-125LTN，lattice专业户，现货支持
德信电子（香港）有限公司 客服经理：林先生 联系电话：0755-33359577
2019-7-22ISPLSI1016E-80LJN，lattice专业户，现货支持
德信电子（香港）有限公司 客服经理：林先生 联系电话：0755-33359577
2019-7-22
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