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IS43D价格
参考价格：￥36.7279
型号：IS43DR16160A-37CBL 品牌：ISSI 备注：这里有IS43D多少钱，2026年最近7天走势，今日出价，今日竞价，IS43D批发/采购报价，IS43D行情走势销售排行榜，IS43D报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
1.8V DDR2 SDRAM ·Single supply voltage of 1.8V ± 0.1V\n·SSTL_18 compatible inputs\n·Data masking per byte on Write commands\n·Programmable burst length of 4 or 8\n·Programmable CAS Latency of 3, 4, 5 or 6\n·Auto-Refresh and Self-Refresh Modes\n·OCD (Off-Chip Driver Impedance Adjustment)\n·ODT (On Die Termination) s | ISSI 矽成半导体 |   | ||
1.8V DDR2 SDRAM ·Single supply voltage of 1.8V ± 0.1V\n·SSTL_18 compatible inputs\n·Data masking per byte on Write commands\n·Programmable burst length of 4 or 8\n·Programmable CAS Latency of 3, 4, 5 or 6\n·Auto-Refresh and Self-Refresh Modes\n·OCD (Off-Chip Driver Impedance Adjustment)\n·ODT (On Die Termination) s | ISSI 矽成半导体 | | ||
1.8V DDR2 SDRAM ·Single supply voltage of 1.8V ± 0.1V\n·SSTL_18 compatible inputs\n·Data masking per byte on Write commands\n·Programmable burst length of 4 or 8\n·Programmable CAS Latency of 3, 4, 5 or 6\n·Auto-Refresh and Self-Refresh Modes\n·OCD (Off-Chip Driver Impedance Adjustment)\n·ODT (On Die Termination) s | ISSI 矽成半导体 | | ||
256Mx8, 128Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 8 inte | ISSI 矽成半导体 | | ||
256Mx8, 128Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 8 inte | ISSI 矽成半导体 | | ||
256Mx8, 128Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 8 inte | ISSI 矽成半导体 | | ||
256Mx8, 128Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 8 inte | ISSI 矽成半导体 | | ||
256Mx8, 128Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 8 inte | ISSI 矽成半导体 | | ||
256Mx8, 128Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 8 inte | ISSI 矽成半导体 | | ||
16Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | | ||
16Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | | ||
16Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | | ||
16Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | | ||
16Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | | ||
16Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | | ||
16Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | | ||
16Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | | ||
16Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | | ||
16Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | | ||
64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | | ||
64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | | ||
64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | | ||
64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | | ||
64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | | ||
64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | | ||
64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | | ||
64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | | ||
64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | | ||
64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | | ||
64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | | ||
64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | | ||
64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | | ||
1Gb (x8, x16) DDR2 SDRAM FEATURES Clock frequency up to 400MHz 8 internal banks for concurrent operation 4-bit prefetch architecture Programmable CAS Latency: 3, 4, 5, 6 and 7 Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6 Write Latency = Read Latency-1 Programmable Burst Sequence: Sequential o | ISSI 矽成半导体 | | ||
1Gb (x8, x16) DDR2 SDRAM FEATURES Clock frequency up to 400MHz 8 internal banks for concurrent operation 4‐bit prefetch architecture Programmable CAS Latency: 3, 4, 5, 6 and 7 Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6 Write Latency = Read Latency‐1 Programmable Burst Sequence: Sequential | ISSI 矽成半导体 | | ||
1Gb (x8, x16) DDR2 SDRAM FEATURES Clock frequency up to 400MHz 8 internal banks for concurrent operation 4‐bit prefetch architecture Programmable CAS Latency: 3, 4, 5, 6 and 7 Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6 Write Latency = Read Latency‐1 Programmable Burst Sequence: Sequential | ISSI 矽成半导体 | | ||
1Gb (x8, x16) DDR2 SDRAM FEATURES Clock frequency up to 400MHz 8 internal banks for concurrent operation 4-bit prefetch architecture Programmable CAS Latency: 3, 4, 5, 6 and 7 Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6 Write Latency = Read Latency-1 Programmable Burst Sequence: Sequential o | ISSI 矽成半导体 | | ||
1Gb (x8, x16) DDR2 SDRAM FEATURES Clock frequency up to 400MHz 8 internal banks for concurrent operation 4-bit prefetch architecture Programmable CAS Latency: 3, 4, 5, 6 and 7 Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6 Write Latency = Read Latency-1 Programmable Burst Sequence: Sequential o | ISSI 矽成半导体 | | ||
1Gb (x8, x16) DDR2 SDRAM FEATURES Clock frequency up to 400MHz 8 internal banks for concurrent operation 4‐bit prefetch architecture Programmable CAS Latency: 3, 4, 5, 6 and 7 Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6 Write Latency = Read Latency‐1 Programmable Burst Sequence: Sequential | ISSI 矽成半导体 | | ||
1Gb (x8, x16) DDR2 SDRAM FEATURES Clock frequency up to 400MHz 8 internal banks for concurrent operation 4‐bit prefetch architecture Programmable CAS Latency: 3, 4, 5, 6 and 7 Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6 Write Latency = Read Latency‐1 Programmable Burst Sequence: Sequential | ISSI 矽成半导体 | | ||
1Gb (x8, x16) DDR2 SDRAM FEATURES Clock frequency up to 400MHz 8 internal banks for concurrent operation 4‐bit prefetch architecture Programmable CAS Latency: 3, 4, 5, 6 and 7 Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6 Write Latency = Read Latency‐1 Programmable Burst Sequence: Sequential | ISSI 矽成半导体 | | ||
1Gb (x8, x16) DDR2 SDRAM FEATURES Clock frequency up to 400MHz 8 internal banks for concurrent operation 4‐bit prefetch architecture Programmable CAS Latency: 3, 4, 5, 6 and 7 Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6 Write Latency = Read Latency‐1 Programmable Burst Sequence: Sequential | ISSI 矽成半导体 | | ||
1Gb (x8, x16) DDR2 SDRAM FEATURES Clock frequency up to 400MHz 8 internal banks for concurrent operation 4-bit prefetch architecture Programmable CAS Latency: 3, 4, 5, 6 and 7 Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6 Write Latency = Read Latency-1 Programmable Burst Sequence: Sequential o | ISSI 矽成半导体 | | ||
1Gb (x8, x16) DDR2 SDRAM FEATURES Clock frequency up to 400MHz 8 internal banks for concurrent operation 4-bit prefetch architecture Programmable CAS Latency: 3, 4, 5, 6 and 7 Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6 Write Latency = Read Latency-1 Programmable Burst Sequence: Sequential o | ISSI 矽成半导体 | | ||
1Gb (x8, x16) DDR2 SDRAM FEATURES Clock frequency up to 400MHz 8 internal banks for concurrent operation 4‐bit prefetch architecture Programmable CAS Latency: 3, 4, 5, 6 and 7 Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6 Write Latency = Read Latency‐1 Programmable Burst Sequence: Sequential | ISSI 矽成半导体 | | ||
1Gb (x8, x16) DDR2 SDRAM FEATURES Clock frequency up to 400MHz 8 internal banks for concurrent operation 4‐bit prefetch architecture Programmable CAS Latency: 3, 4, 5, 6 and 7 Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6 Write Latency = Read Latency‐1 Programmable Burst Sequence: Sequential | ISSI 矽成半导体 | | ||
1Gb (x8, x16) DDR2 SDRAM FEATURES Clock frequency up to 400MHz 8 internal banks for concurrent operation 4-bit prefetch architecture Programmable CAS Latency: 3, 4, 5, 6 and 7 Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6 Write Latency = Read Latency-1 Programmable Burst Sequence: Sequential o | ISSI 矽成半导体 | | ||
1Gb (x8, x16) DDR2 SDRAM FEATURES Clock frequency up to 400MHz 8 internal banks for concurrent operation 4-bit prefetch architecture Programmable CAS Latency: 3, 4, 5, 6 and 7 Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6 Write Latency = Read Latency-1 Programmable Burst Sequence: Sequential o | ISSI 矽成半导体 | | ||
1Gb (x8, x16) DDR2 SDRAM FEATURES Clock frequency up to 400MHz 8 internal banks for concurrent operation 4-bit prefetch architecture Programmable CAS Latency: 3, 4, 5, 6 and 7 Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6 Write Latency = Read Latency-1 Programmable Burst Sequence: Sequential o | ISSI 矽成半导体 | | ||
1Gb (x8, x16) DDR2 SDRAM FEATURES Clock frequency up to 400MHz 8 internal banks for concurrent operation 4-bit prefetch architecture Programmable CAS Latency: 3, 4, 5, 6 and 7 Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6 Write Latency = Read Latency-1 Programmable Burst Sequence: Sequential o | ISSI 矽成半导体 | | ||
128Mx8, 64Mx16 DDR2 DRAM FEATURES • Standard Voltage: Vdd and Vddq = 1.8V ±0.1V • Low Voltage (L): Vdd and Vddq = 1.5V ±0.075V • SSTL_18-compatible for Standard Voltage • SSTL_15-compatible for Low Voltage • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bi | ISSI 矽成半导体 | | ||
128Mx8, 64Mx16 DDR2 DRAM FEATURES • Standard Voltage: Vdd and Vddq = 1.8V ±0.1V • Low Voltage (L): Vdd and Vddq = 1.5V ±0.075V • SSTL_18-compatible for Standard Voltage • SSTL_15-compatible for Low Voltage • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bi | ISSI 矽成半导体 | | ||
128Mx8, 64Mx16 DDR2 DRAM FEATURES • Standard Voltage: Vdd and Vddq = 1.8V ±0.1V • Low Voltage (L): Vdd and Vddq = 1.5V ±0.075V • SSTL_18-compatible for Standard Voltage • SSTL_15-compatible for Low Voltage • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bi | ISSI 矽成半导体 | | ||
128Mx8, 64Mx16 DDR2 DRAM FEATURES • Standard Voltage: Vdd and Vddq = 1.8V ±0.1V • Low Voltage (L): Vdd and Vddq = 1.5V ±0.075V • SSTL_18-compatible for Standard Voltage • SSTL_15-compatible for Low Voltage • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bi | ISSI 矽成半导体 | | ||
128Mx8, 64Mx16 DDR2 DRAM FEATURES • Standard Voltage: Vdd and Vddq = 1.8V ±0.1V • Low Voltage (L): Vdd and Vddq = 1.5V ±0.075V • SSTL_18-compatible for Standard Voltage • SSTL_15-compatible for Low Voltage • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bi | ISSI 矽成半导体 | | ||
128Mx8, 64Mx16 DDR2 DRAM FEATURES • Standard Voltage: Vdd and Vddq = 1.8V ±0.1V • Low Voltage (L): Vdd and Vddq = 1.5V ±0.075V • SSTL_18-compatible for Standard Voltage • SSTL_15-compatible for Low Voltage • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bi | ISSI 矽成半导体 | | ||
128Mx8, 64Mx16 DDR2 DRAM FEATURES • Standard Voltage: Vdd and Vddq = 1.8V ±0.1V • Low Voltage (L): Vdd and Vddq = 1.5V ±0.075V • SSTL_18-compatible for Standard Voltage • SSTL_15-compatible for Low Voltage • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bi | ISSI 矽成半导体 | | ||
128Mx8, 64Mx16 DDR2 DRAM FEATURES • Standard Voltage: Vdd and Vddq = 1.8V ±0.1V • Low Voltage (L): Vdd and Vddq = 1.5V ±0.075V • SSTL_18-compatible for Standard Voltage • SSTL_15-compatible for Low Voltage • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bi | ISSI 矽成半导体 | | ||
8Mx32 256Mb DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | | ||
8Mx32 256Mb DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | | ||
8Mx32 256Mb DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte | ISSI 矽成半导体 | |
IS43D产品属性
- 类型
描述
- 型号
IS43D
- 制造商
IDEC Corporation
- 制造商
IDEC Corporation
- 功能描述
SENS.IND. 10-30VDC NPN NO NC
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
ISSI |
24+ |
TSSOP-8 |
9600 |
原装现货,优势供应,支持实单! |
|||
ISSI |
23+ |
MSOP8 |
4708 |
一级代理原厂VIP渠道,专注军工、汽车、医疗、工业、 |
|||
ISSI |
25+ |
SOP8 |
15000 |
全新原装现货,价格优势 |
|||
ISSI |
25+ |
MSOP8 |
220 |
百分百原装正品 真实公司现货库存 本公司只做原装 可 |
|||
ISSI |
2447 |
TSSOP-8 |
100500 |
一级代理专营品牌!原装正品,优势现货,长期排单到货 |
|||
ISSI |
23+ |
MSOP8 |
8000 |
只做原装现货 |
|||
23+ |
TSOP |
54198 |
##公司主营品牌长期供应100%原装现货可含税提供技术 |
||||
原装 |
最新 |
MSOP8 |
12600 |
||||
ISSI |
23+ |
MSOP8 |
50000 |
全新原装正品现货,支持订货 |
|||
ISSI |
24+ |
MSOP8 |
56 |
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IS43D规格书下载地址
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- k2010
- jumper
- jtag接口
- jk触发器
- j111
- j108
- isd1420
- IS489
- IS488
- IS487
- IS486
- IS485
- IS482
- IS481
- IS480P
- IS-480
- IS474
- IS471FE
- IS471F
- IS457
- IS456
- IS455
- IS452
- IS450
- IS445
- IS440F
- IS440
- IS43LD16640A-3BL
- IS43DR86400D-3DBLI
- IS43DR86400D-25DBLI
- IS43DR16640B-3DBLI
- IS43DR16640B-3DBL
- IS43DR16640B-3DBI
- IS43DR16640B-25DBLI
- IS43DR16640B-25DBL
- IS43DR16320D-3DBL
- IS43DR16320D-25DBLI
- IS43DR16320D-25DBL
- IS43DR16320C-3DBLI
- IS43DR16320C-3DBL
- IS43DR16320C-25DBLI
- IS43DR16320C-25DBL
- IS43DR16160B-37CBLI
- IS43DR16160B-37CBL
- IS43DR16160B-25DBLI-TR
- IS43DR16160A-37CBLI
- IS43DR16160A-37CBL
- IS438
- IS437
- IS436
- IS435
- IS432
- IS431
- IS42VM32800E-6BLI
- IS42VM32160D-75BLI
- IS42VM16800G-75BLI
- IS42VM16400K-75BLI
- IS42VM16160K-75BLI
- IS42SM32400G-75BLI
- IS42SM32160C-75BLI
- IS42SM16400K-75BLI
- IS42SM
- IS42S86400D-7TLI
- IS42S86400D-7TL
- IS42S86400D-6TLI
- IS42S86400B-7TL-TR
- IS42S86400B-7TLI
- IS42S86400B-7TL
- IS42S83200G-7TLI
- IS42S83200G-7TL
- IS42S81600F-7TLI
- IS42S81600F-7TL
- IS42S81600E-7TL
- IS42S32800J-7TLI
- IS423
- IS422
- IS421
- IS420
- IS4100
- IS3H7
- IS3H4
- IS3H&K
- IS3H&J
- IS3H&I
- IS3H&H
- IS3H&GR
- IS3H&GB
IS43D数据表相关新闻
IS42S32800J-7TLI保原装支持检测
IS42S32800J-7TLI保原装支持检测
2025-7-3IS42S32800J-7TL
IS42S32800J-7TL
2022-12-1IS43DR82560B-25EBL
IS43DR82560B-25EBL
2021-7-8IS42S32800J-6TLI
IS42S32800J-6TLI TJA1051T/1 ISL9237HRZ-T XC6SLX75-2FGG484I XC6223D181MR-G XC95108-20TQ100I XC6SLX16-3CSG225I CY7C433-20AXC XC6SLX45-2FGG484I LXCRP1C1BL1N LXCRN1C1CL1N XCR3512XL-12PQ208I XC6SLX45-3FGG676I XC7A100T-2CSG324I XC6SLX150T-3CSG484C XC6SLX16-3CSG
2021-6-25IS43DR82560B-25EBL
IS43DR82560B-25EBL
2021-6-2IS43DR82560B-25EBL
IS43DR82560B-25EBL
2021-6-2
DdatasheetPDF页码索引
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