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IS43D价格

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型号：IS43DR16160A-37CBL 品牌：ISSI 备注：这里有IS43D多少钱，2026年最近7天走势，今日出价，今日竞价，IS43D批发/采购报价，IS43D行情走势销售排行榜，IS43D报价。

型号	功能描述	生产厂家企业	LOGO
IS43DR16128C	256Mx8, 128Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 8 inte	ISSI 矽成半导体	ISSI
IS43DR16128C-25DBL	256Mx8, 128Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 8 inte	ISSI 矽成半导体	ISSI
IS43DR16128C-25DBLI	256Mx8, 128Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 8 inte	ISSI 矽成半导体	ISSI
IS43DR16128C-3DBI	256Mx8, 128Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 8 inte	ISSI 矽成半导体	ISSI
IS43DR16128C-3DBL	256Mx8, 128Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 8 inte	ISSI 矽成半导体	ISSI
IS43DR16128C-3DBLI	256Mx8, 128Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 8 inte	ISSI 矽成半导体	ISSI
IS43DR16160B	16Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte	ISSI 矽成半导体	ISSI
IS43DR16160B-25DBI	16Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte	ISSI 矽成半导体	ISSI
IS43DR16160B-25DBL	16Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte	ISSI 矽成半导体	ISSI
IS43DR16160B-25DBLI	16Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte	ISSI 矽成半导体	ISSI
IS43DR16160B-37CBI	16Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte	ISSI 矽成半导体	ISSI
IS43DR16160B-37CBL	16Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte	ISSI 矽成半导体	ISSI
IS43DR16160B-37CBLI	16Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte	ISSI 矽成半导体	ISSI
IS43DR16160B-3DBI	16Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte	ISSI 矽成半导体	ISSI
IS43DR16160B-3DBL	16Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte	ISSI 矽成半导体	ISSI
IS43DR16160B-3DBLI	16Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte	ISSI 矽成半导体	ISSI
IS43DR16320D	64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte	ISSI 矽成半导体	ISSI
IS43DR16320D-25DBI	64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte	ISSI 矽成半导体	ISSI
IS43DR16320D-25DBL	64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte	ISSI 矽成半导体	ISSI
IS43DR16320D-25DBLI	64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte	ISSI 矽成半导体	ISSI
IS43DR16320E-25DBI	64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte	ISSI 矽成半导体	ISSI
IS43DR16320E-25DBL	64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte	ISSI 矽成半导体	ISSI
IS43DR16320E-25DBLI	64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte	ISSI 矽成半导体	ISSI
IS43DR16320E-3DBI	64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte	ISSI 矽成半导体	ISSI
IS43DR16320E-3DBL	64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte	ISSI 矽成半导体	ISSI
IS43DR16320E-3DBLI	64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte	ISSI 矽成半导体	ISSI
IS43DR16640B-25DBI	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4‐bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency‐1  Programmable Burst Sequence: Sequential	ISSI 矽成半导体	ISSI
IS43DR16640B-25DBI	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4-bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency-1  Programmable Burst Sequence: Sequential o	ISSI 矽成半导体	ISSI
IS43DR16640B-25DBL	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4‐bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency‐1  Programmable Burst Sequence: Sequential	ISSI 矽成半导体	ISSI
IS43DR16640B-25DBL	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4-bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency-1  Programmable Burst Sequence: Sequential o	ISSI 矽成半导体	ISSI
IS43DR16640B-25DBLI	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4‐bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency‐1  Programmable Burst Sequence: Sequential	ISSI 矽成半导体	ISSI
IS43DR16640B-25DBLI	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4-bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency-1  Programmable Burst Sequence: Sequential o	ISSI 矽成半导体	ISSI
IS43DR16640B-25EBL	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4‐bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency‐1  Programmable Burst Sequence: Sequential	ISSI 矽成半导体	ISSI
IS43DR16640B-25EBLI	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4‐bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency‐1  Programmable Burst Sequence: Sequential	ISSI 矽成半导体	ISSI
IS43DR16640B-3DBI	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4‐bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency‐1  Programmable Burst Sequence: Sequential	ISSI 矽成半导体	ISSI
IS43DR16640B-3DBI	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4-bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency-1  Programmable Burst Sequence: Sequential o	ISSI 矽成半导体	ISSI
IS43DR16640B-3DBL	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4‐bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency‐1  Programmable Burst Sequence: Sequential	ISSI 矽成半导体	ISSI
IS43DR16640B-3DBL	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4-bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency-1  Programmable Burst Sequence: Sequential o	ISSI 矽成半导体	ISSI
IS43DR16640B-3DBLI	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4‐bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency‐1  Programmable Burst Sequence: Sequential	ISSI 矽成半导体	ISSI
IS43DR16640B-3DBLI	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4-bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency-1  Programmable Burst Sequence: Sequential o	ISSI 矽成半导体	ISSI
IS43DR16640BL-25DBL	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4-bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency-1  Programmable Burst Sequence: Sequential o	ISSI 矽成半导体	ISSI
IS43DR16640BL-3DBL	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4-bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency-1  Programmable Burst Sequence: Sequential o	ISSI 矽成半导体	ISSI
IS43DR16640BL-3DBLI	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4-bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency-1  Programmable Burst Sequence: Sequential o	ISSI 矽成半导体	ISSI
IS43DR16640D-18FBL	128Mx8, 64Mx16 DDR2 DRAM FEATURES • Standard Voltage: Vdd and Vddq = 1.8V ±0.1V • Low Voltage (L): Vdd and Vddq = 1.5V ±0.075V • SSTL_18-compatible for Standard Voltage • SSTL_15-compatible for Low Voltage • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bi	ISSI 矽成半导体	ISSI
IS43DR16640D-18FBLI	128Mx8, 64Mx16 DDR2 DRAM FEATURES • Standard Voltage: Vdd and Vddq = 1.8V ±0.1V • Low Voltage (L): Vdd and Vddq = 1.5V ±0.075V • SSTL_18-compatible for Standard Voltage • SSTL_15-compatible for Low Voltage • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bi	ISSI 矽成半导体	ISSI
IS43DR81280B	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4-bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency-1  Programmable Burst Sequence: Sequential o	ISSI 矽成半导体	ISSI
IS43DR81280B-25DBL	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4-bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency-1  Programmable Burst Sequence: Sequential o	ISSI 矽成半导体	ISSI
IS43DR81280B-25DBLI	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4‐bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency‐1  Programmable Burst Sequence: Sequential	ISSI 矽成半导体	ISSI
IS43DR81280B-25DBLI	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4-bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency-1  Programmable Burst Sequence: Sequential o	ISSI 矽成半导体	ISSI
IS43DR81280B-25EBL	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4‐bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency‐1  Programmable Burst Sequence: Sequential	ISSI 矽成半导体	ISSI
IS43DR81280B-25EBLI	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4‐bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency‐1  Programmable Burst Sequence: Sequential	ISSI 矽成半导体	ISSI
IS43DR81280B-3DBI	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4‐bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency‐1  Programmable Burst Sequence: Sequential	ISSI 矽成半导体	ISSI
IS43DR81280B-3DBI	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4-bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency-1  Programmable Burst Sequence: Sequential o	ISSI 矽成半导体	ISSI
IS43DR81280B-3DBL	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4‐bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency‐1  Programmable Burst Sequence: Sequential	ISSI 矽成半导体	ISSI
IS43DR81280B-3DBL	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4-bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency-1  Programmable Burst Sequence: Sequential o	ISSI 矽成半导体	ISSI
IS43DR81280B-3DBLI	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4‐bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency‐1  Programmable Burst Sequence: Sequential	ISSI 矽成半导体	ISSI
IS43DR81280B-3DBLI	1Gb (x8, x16) DDR2 SDRAM FEATURES  Clock frequency up to 400MHz  8 internal banks for concurrent operation  4-bit prefetch architecture  Programmable CAS Latency: 3, 4, 5, 6 and 7  Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6  Write Latency = Read Latency-1  Programmable Burst Sequence: Sequential o	ISSI 矽成半导体	ISSI
IS43DR82560C-25DBL	256Mx8, 128Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 8 inte	ISSI 矽成半导体	ISSI
IS43DR82560C-25DBLI	256Mx8, 128Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 8 inte	ISSI 矽成半导体	ISSI
IS43DR82560C-3DBLI	256Mx8, 128Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 8 inte	ISSI 矽成半导体	ISSI

IS43D产品属性

类型
描述
型号
IS43D
制造商
IDEC Corporation
制造商
IDEC Corporation
功能描述
SENS.IND. 10-30VDC NPN NO NC

IS43D供应商更多...

更新时间：2026-3-2 14:07:00

IC供应商	芯片型号	品牌	批号	封装	库存	备注	价格
深圳市华来深电子有限公司	IS43DR16128C-25DBLI	ISSI	23+	BGA84	8600	受权代理!全新原装现货特价热卖!	询价
深圳市威雅利发展有限公司	IS43DR16128C-3DBLI	ISSI	17+	BGA	20	一级代理,专注军工、汽车、医疗、工业、新能源、电力	询价
深圳市拓亿芯电子有限公司	IS43DR16128C-25DBL	ISSI	25+	BGA84	30000	代理全新原装现货,价格优势	询价
深圳市诺美思科技有限公司	IS43DR16128C-3DBLI	ISSI		原厂封装	9800	原装进口公司现货假一赔百	询价
深圳市科恒伟业电子有限公司	IS43DR16128C-25DBLI	ISSI/芯成	2450+	BGA84	8850	只做原装正品假一赔十为客户做到零风险!!	询价
深圳市英科美电子有限公司	IS43DR16128C-25DBLI	ISSI	2223+	BGA84	26800	只做原装正品假一赔十为客户做到零风险	询价
深圳市粤骏腾电子科技有限公司	IS43DR16128C-25DBLI	ISSI	24+	BGA84	5000	十年沉淀唯有原装	询价
标准国际(香港)有限公司	IS43DR16128C25DBL	ISSI	25+		10	公司优势库存热卖中!	询价
深圳市河锋鑫科技有限公司	IS43DR16128C3DBLITR	ISSI Integrated Silicon Soluti	22+	84TWBGA (8x12.5)	9000	原厂渠道,现货配单	询价
深圳市博中泰实业有限公司	IS43DR16128C-25DBLI-TR	ISSI/芯成	24+	BGA-84	60000		询价

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IS43D价格

IS43D产品属性

IS43D供应商更多...

IS43D芯片相关品牌

IS43D规格书下载地址

IS43D参数引脚图相关

IS43D数据表相关新闻

IS42S32800J-7TLI保原装支持检测

IS42S32800J-7TL

IS43DR82560B-25EBL

IS42S32800J-6TLI

IS43DR82560B-25EBL

IS43DR82560B-25EBL

DdatasheetPDF页码索引