64Mx8, 32Mx16 DDR2 DRAM

FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte

Differential data strobe

文件：1.65495 Mbytes Page：48 Pages

1.8V DDR2 SDRAM

Clock frequency up to 400MHz

文件：867 Kbytes Page：29 Pages

64Mx8, 32Mx16 DDR2 DRAM

FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte

64Mx8, 32Mx16 DDR2 DRAM

FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte

64Mx8, 32Mx16 DDR2 DRAM

FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.8V I/O (SSTL_18-compatible) • Double data rate interface: two data transfers per clock cycle • Differential data strobe (DQS, DQS) • 4-bit prefetch architecture • On chip DLL to align DQ and DQS transitions with CK • 4 inte

封装/外壳：84-TFBGA 包装：卷带（TR） 描述：IC DRAM 512MBIT PARALLEL 84TWBGA 集成电路（IC） 存储器

封装/外壳：84-TFBGA 包装：管件 描述：IC DRAM 512MBIT PARALLEL 84TWBGA 集成电路（IC） 存储器