LVDS, 1:4 Clock Buffer Terabuffer™

Features • Guaranteed low skew: 50ps (maximum) • Very low duty cycle distortion: 125ps (maximum) • Propagation delay: 1.75ns (maximum) • Up to 450MHz operation • Selectable inputs • Hot insertable and over-voltage tolerant inputs • 3.3V/2.5V LVTTL, HSTL eHSTL, LVEPECL (2.5V), LVPECL (3.3V)

LVDS, 1:4 Clock Buffer Terabuffer™

General Description The 5T9304I differential clock buffer is a user-selectable differential input to four LVDS outputs. The fanout from a differential input to four LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The 5T9304I can act as

LVDS, 1:4 Clock Buffer Terabuffer

文件：180.36 Kbytes Page：16 Pages

LVDS, 1:4 Clock Buffer Terabuffer

文件：153.31 Kbytes Page：17 Pages

LVDS, 1:4 Clock Buffer Terabuffer

文件：153.31 Kbytes Page：17 Pages