3.3V ZERO DELAY CLOCK MULTIPLIER

DESCRIPTION: The IDT2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC CLOCK MULT ZD STD DRV 16-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3V ZERO DELAY CLOCK MULTIPLIER

DESCRIPTION: The IDT2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC CLOCK MULT ZD STD DRV 16-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3V ZERO DELAY CLOCK MULTIPLIER

DESCRIPTION: The IDT2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range

3.3V ZERO DELAY CLOCK MULTIPLIER

DESCRIPTION: The IDT2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range

3.3V ZERO DELAY CLOCK MULTIPLIER

FEATURES: • Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 133MHz operating frequency • Distributes one clock input to two banks of four outputs • Separate output enable for each output bank • External feedback (FBK) pin is used to synchronize the outputs to the cl

3.3V ZERO DELAY CLOCK MULTIPLIER

DESCRIPTION: The IDT2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range