첨1/첨2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR

文件：260.47 Kbytes Page：14 Pages

첨1/첨2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR

文件：260.47 Kbytes Page：14 Pages

첨1/첨2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR

文件：260.47 Kbytes Page：14 Pages

÷1/÷2 Differential-to-LVDS Clock Generator

FEATURES • One differential LVDS output • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVDS

÷1/÷2 Differential-to-LVDS Clock Generator

FEATURES • One differential LVDS output • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVDS

÷1/÷2 Differential-to-LVDS Clock Generator

FEATURES • One differential LVDS output • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVDS