÷1/÷2 Differential-to-LVDS Clock Generator

FEATURES • One differential LVDS output • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVDS

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：托盘 描述：IC CLK GEN DIFF-LVDS 8-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

÷1/÷2 Differential-to-LVDS Clock Generator

FEATURES • One differential LVDS output • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVDS

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：卷带（TR） 描述：IC CLOCK GEN LVDS 8-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

÷1/÷2 Differential-to-LVDS Clock Generator

FEATURES • One differential LVDS output • One differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum clock input frequency: 1GHz • Translates any single ended input signal (LVCMOS, LVTTL, GTL) to LVDS

첨1/첨2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR

文件：260.47 Kbytes Page：14 Pages

첨1/첨2 DIFFERENTIAL-TO-LVDS CLOCK GENERATOR

文件：260.47 Kbytes Page：14 Pages