2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER

GENERAL DESCRIPTION The ICS85356I is a dual 2:1 Differential-to-LVPECL Multiplexer and is a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The device has both common select and individual select inputs. When COM_SEL is logic High, the CLKxx input pairs will be pa

2:1, DIFFERENTIAL-TO-3.3V DUAL LVPECL / ECL CLOCK MULTIPLEXER

GENERAL DESCRIPTION The ICS85356I is a dual 2:1 Differential-to-LVPECL Multiplexer and is a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The device has both common select and individual select inputs. When COM_SEL is logic High, the CLKxx input pairs will be pa

2:1, Differential-to-3.3V Dual LVPECL/ECL Clock Multiplexer

Features • High speed differential muliplexer. The device can be configured as a 2:1 multiplexer • Dual 3.3V LVPECL outputs • Selectable differential CLKx/nCLKx input pairs • Differential CLKx/nCLKx pairs can accept the following interface levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Output f

2:1, Differential-to-3.3V Dual LVPECL/ECL Clock Multiplexer

Features • High speed differential muliplexer. The device can be configured as a 2:1 multiplexer • Dual 3.3V LVPECL outputs • Selectable differential CLKx/nCLKx input pairs • Differential CLKx/nCLKx pairs can accept the following interface levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Output f

2:1, Differential-to-3.3V Dual LVPECL/ECL Clock Multiplexer

Features • High speed differential muliplexer. The device can be configured as a 2:1 multiplexer • Dual 3.3V LVPECL outputs • Selectable differential CLKx/nCLKx input pairs • Differential CLKx/nCLKx pairs can accept the following interface levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Output f

2:1, Differential-to-3.3V Dual LVPECL/ECL Clock Multiplexer

Features • High speed differential muliplexer. The device can be configured as a 2:1 multiplexer • Dual 3.3V LVPECL outputs • Selectable differential CLKx/nCLKx input pairs • Differential CLKx/nCLKx pairs can accept the following interface levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Output f

Propagation delay

文件：611.27 Kbytes Page：15 Pages