2:1, Differential-to-3.3V Dual LVPECL/ECL Clock Multiplexer

Features • High speed differential muliplexer. The device can be configured as a 2:1 multiplexer • Dual 3.3V LVPECL outputs • Selectable differential CLKx/nCLKx input pairs • Differential CLKx/nCLKx pairs can accept the following interface levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Output f

封装/外壳：20-SOIC（0.295"，7.50mm 宽） 包装：卷带（TR） 描述：IC CLK MULTPLX 2:1 900MHZ 20SOIC 集成电路（IC） 时钟缓冲器，驱动器

2:1, Differential-to-3.3V Dual LVPECL/ECL Clock Multiplexer

Features • High speed differential muliplexer. The device can be configured as a 2:1 multiplexer • Dual 3.3V LVPECL outputs • Selectable differential CLKx/nCLKx input pairs • Differential CLKx/nCLKx pairs can accept the following interface levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Output f

Propagation delay

文件：611.27 Kbytes Page：15 Pages

2:1, Differential-to-3.3V Dual LVPECL/ECL Clock Multiplexer

Features • High speed differential muliplexer. The device can be configured as a 2:1 multiplexer • Dual 3.3V LVPECL outputs • Selectable differential CLKx/nCLKx input pairs • Differential CLKx/nCLKx pairs can accept the following interface levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Output f

封装/外壳：20-SOIC（0.295"，7.50mm 宽） 包装：卷带（TR） 描述：IC CLK MULTPLX 2:1 900MHZ 20SOIC 集成电路（IC） 时钟缓冲器，驱动器

2:1, Differential-to-3.3V Dual LVPECL/ECL Clock Multiplexer

Features • High speed differential muliplexer. The device can be configured as a 2:1 multiplexer • Dual 3.3V LVPECL outputs • Selectable differential CLKx/nCLKx input pairs • Differential CLKx/nCLKx pairs can accept the following interface levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Output f

2:1, Differential-to-3.3V Dual LVPECL/ECL Clock Multiplexer

Features • High speed differential muliplexer. The device can be configured as a 2:1 multiplexer • Dual 3.3V LVPECL outputs • Selectable differential CLKx/nCLKx input pairs • Differential CLKx/nCLKx pairs can accept the following interface levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Output f