Dual D-type Flip Flops with Preset and Clear

Description The HD74LVC74 has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package. The logic level present at the data input is transferred to the output during the positive going transition of the clock pulse. Preset and clear are independent of the clock and ac

Dual D-type Flip Flops with Preset and Clear

Description The HD74LVC74 has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package. The logic level present at the data input is transferred to the output during the positive going transition of the clock pulse. Preset and clear are independent of the clock and ac

Dual D-type Flip Flops with Preset and Clear

Standard IC>General-Purpose Logics>HD/RD74LVC Series

Dual D-type Flip Flops with Preset and Clear

Description The HD74LVC74 has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package. The logic level present at the data input is transferred to the output during the positive going transition of the clock pulse. Preset and clear are independent of the clock and ac

Dual D-type Flip Flops with Preset and Clear

Description The HD74LVC74 has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package. The logic level present at the data input is transferred to the output during the positive going transition of the clock pulse. Preset and clear are independent of the clock and ac

General-Purpose Logics-RD74LVC-B Series

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input

Dual D-type flip-flop with set and reset; positive-edge trigger

Dual D-type flip-flop with set and reset; positive-edge trigger

DESCRIPTION The 74LVC74A is a high-performance, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES •Wide supply voltage range of 1.2 V to 3.6 V •In accordance with JEDEC standard no. 8-1A. •Inputs accept voltages up to 5.5 V •CMOS low power c

Dual D-type flip-flop with set and reset; positive-edge trigger

Dual D-type flip-flop with set and reset; positive-edge trigger

1. General description The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input