位置:首页 > IC中文资料第1099页 > HD74LVC74
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
HD74LVC74 | Dual D-type Flip Flops with Preset and Clear Description The HD74LVC74 has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package. The logic level present at the data input is transferred to the output during the positive going transition of the clock pulse. Preset and clear are independent of the clock and ac | HitachiHitachi Semiconductor 日立日立公司 | ||
HD74LVC74 | Dual D-type Flip Flops with Preset and Clear Description The HD74LVC74 has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package. The logic level present at the data input is transferred to the output during the positive going transition of the clock pulse. Preset and clear are independent of the clock and ac | RENESAS 瑞萨 | ||
HD74LVC74 | Dual D-type Flip Flops with Preset and Clear | HitachiHitachi Semiconductor 日立日立公司 | ||
HD74LVC74 | Standard IC>General-Purpose Logics>HD/RD74LVC Series | RENESAS 瑞萨 | ||
Dual D-type Flip Flops with Preset and Clear Description The HD74LVC74 has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package. The logic level present at the data input is transferred to the output during the positive going transition of the clock pulse. Preset and clear are independent of the clock and ac | RENESAS 瑞萨 | |||
Dual D-type Flip Flops with Preset and Clear Description The HD74LVC74 has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package. The logic level present at the data input is transferred to the output during the positive going transition of the clock pulse. Preset and clear are independent of the clock and ac | RENESAS 瑞萨 | |||
General-Purpose Logics-RD74LVC-B Series | RENESAS 瑞萨 | |||
Dual D-type flip-flop with set and reset; positive-edge trigger 1. General description The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input | NEXPERIA 安世 | |||
Dual D-type flip-flop with set and reset; positive-edge trigger | ETC 知名厂家 | ETC | ||
Dual D-type flip-flop with set and reset; positive-edge trigger DESCRIPTION The 74LVC74A is a high-performance, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. FEATURES •Wide supply voltage range of 1.2 V to 3.6 V •In accordance with JEDEC standard no. 8-1A. •Inputs accept voltages up to 5.5 V •CMOS low power c | Philips 飞利浦 | |||
Dual D-type flip-flop with set and reset; positive-edge trigger | ETC 知名厂家 | ETC | ||
Dual D-type flip-flop with set and reset; positive-edge trigger 1. General description The 74LVC74A is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input | NEXPERIA 安世 |
HD74LVC74产品属性
- 类型
描述
- 型号
HD74LVC74
- 制造商
Renesas Electronics Corporation
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
RENESAS |
22+ |
TSSOP14 |
8000 |
原装正品支持实单 |
|||
RENESAS/瑞萨 |
23+ |
TSSOP14 |
66600 |
专业芯片配单原装正品假一罚十 |
|||
HITACHI |
2023+ |
SOP-14 |
50000 |
原装现货 |
|||
2023+ |
5800 |
进口原装,现货热卖 |
|||||
RENESAS |
23+ |
TSSOP14 |
7300 |
专注配单,只做原装进口现货 |
|||
HIT |
24+ |
SOP-20/5.2mm |
37500 |
原装正品现货,价格有优势! |
|||
RENESA |
22+ |
SOP5.2 |
20000 |
公司只做原装 品质保障 |
|||
RENESAS/瑞萨 |
2450+ |
SOP5.2 |
8850 |
只做原装正品假一赔十为客户做到零风险!! |
|||
HITACHI/日立 |
2402+ |
TSSOP |
8324 |
原装正品!实单价优! |
|||
RENESAS/瑞萨 |
24+ |
TSSOP14 |
17500 |
郑重承诺只做原装进口现货 |
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