4-bit D-type Register (with 3-state outputs)

Description The four D type Flip-Flops operate synchronously from a common clock. The 3-state outputs allow the device to be used in bus organized systems. The outputs are placed in the 3-stage mode when either of the output disable pins are in the logic high level. The input disable allows the

Quad D-type flip-flop; positive-edge trigger; 3-state

1. General description The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their co

Quad D-type flip-flop; positive-edge trigger; 3-state

GENERAL DESCRIPTION The 74HC/HCT173 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT173 are 4-bit parallel load registers with clock enable control, 3-state buffered outputs (

Quad D-type flip-flop; positive-edge trigger; 3-state

1. General description The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their co

Quad D-type flip-flop; positive-edge trigger; 3-state

GENERAL DESCRIPTION The 74HC/HCT173 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT173 are 4-bit parallel load registers with clock enable control, 3-state buffered outputs (

Quad D-type flip-flop; positive-edge trigger; 3-state

GENERAL DESCRIPTION The 74HC/HCT173 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT173 are 4-bit parallel load registers with clock enable control, 3-state buffered outputs (