Quad D-type flip-flop; positive-edge trigger; 3-state

GENERAL DESCRIPTION The 74HC/HCT173 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT173 are 4-bit parallel load registers with clock enable control, 3-state buffered outputs (

Quad D-type flip-flop; positive-edge trigger; 3-state

1. General description The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their co

Quad D-type flip-flop; positive-edge trigger; 3-state

1. General description The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their co

Quad D-type flip-flop; positive-edge trigger; 3-state

GENERAL DESCRIPTION The 74HC/HCT173 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT173 are 4-bit parallel load registers with clock enable control, 3-state buffered outputs (

74HC173DB - Quad D-type flip-flop; positive-edge trigger; 3-state

Quad D-type flip-flop; positive-edge trigger; 3-state - The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will ·Complies with JEDEC standard no. 7A\n·Input levels:·For 74HC173: CMOS level\n·For 74HCT173: TTL level;

Quad D-type flip-flop; positive-edge trigger; 3-state

The 74HC173-Q100; 74HCT173-Q100 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inp

Quad D-type flip-flop; positive-edge trigger; 3-state

GENERAL DESCRIPTION The 74HC/HCT173 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT173 are 4-bit parallel load registers with clock enable control, 3-state buffered outputs (

Quad D-type flip-flop; positive-edge trigger; 3-state

1. General description The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their co

Quad D-type flip-flop; positive-edge trigger; 3-state

The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inputs that m • Complies with JEDEC standard no. 7A\n• Input levels:• For 74HC173: CMOS level\n• For 74HCT173: TTL level\n\n• Gated input enable for hold (do nothing) mode\n• Gated output enable control mode\n• Edge-triggered D-type register\n• Asynchronous master reset\n• ESD protection:• HBM JESD22-A114F exceed;

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：主复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE SNGL 4BIT 16SO 集成电路（IC） 触发器

封装/外壳：16-SSOP（0.209"，5.30mm 宽） 功能：主复位 包装：管件 描述：IC FF D-TYPE SNGL 4BIT 16SSOP 集成电路（IC） 触发器

QUAD D-TYPE REGISTER 3-STATE

DESCRIPTION The M54/74HC173 is ahigh speedCMOSQUADDTYPE REGISTER (3-STATE) fabricated in silicon gate C2MOS technology. ■ HIGH SPEED fMAX = 73 MHz (TYP.) at VCC = 5 V ■ LOW POWER DISSIPATION ICC = 4 µA (MAX.) at TA = 25 °C ■ HIGH NOISE IMMUNITY VNIH = VNIL = 28 VCC (MIN.)

High Speed CMOS Logic Quad D-Type Flip-Flop, Three-State

文件：57.51 Kbytes Page：10 Pages

High Speed CMOS Logic Quad D-Type Flip-Flop, Three-State

文件：57.51 Kbytes Page：10 Pages