HD74AC Series Common Information

Characteristics • Full logic product line • Industry standard functions and pinouts for SSI and MSI • Meets or exceeds JEDEC standards for HD74ACXX family • TTL inputs on selected circuits • High performance outputs - Common output structure for standard and buffer drivers - Output

HD74AC Series Common Information

Quad 2-Input NAND Gate

Features • Outputs Source/Sink 24 mA

Quad 2-Input NAND Gate

Feature • Outputs Source/Sink 24 mA

Quad 2-Input NAND Gate

Features • Outputs Source/Sink 24 mA

Quad 2-Input NAND Gate

Features • Outputs Source/Sink 24 mA

Quad 2-Input NAND Gate

Features • Outputs Source/Sink 24 mA

Quad 2-Input NAND Gate

Features • Outputs Source/Sink 24 mA

Quad 2-Input NOR Gate

Feature • Outputs Source/Sink 24 mA

Quad 2-Input NAND Gate

Features • Outputs Source/Sink 24 mA

Quad 2-Input NAND Gate

Features • Outputs Source/Sink 24 mA

Quad 2-Input NAND Gate

Features • Outputs Source/Sink 24 mA

Quad 2-Input NAND Gate

Features • Outputs Source/Sink 24 mA

Quad 2-Input NAND Gate

Features • Outputs Source/Sink 24 mA

Hex Inverter

Feature • Outputs Source/Sink 24 mA

Hex Inverter

Features • Outputs Source/Sink 24 mA

Hex Inverter

Features • Outputs Source/Sink 24 mA

Hex Inverter

Features • Outputs Source/Sink 24 mA

Hex Inverter

Features • Outputs Source/Sink 24 mA

Hex Inverter

Features • Outputs Source/Sink 24 mA

Quad 2-Input AND Gate

Quad 2-Input AND Gate Feature • Outputs Source/Sink 24 mA

Quad 2-Input AND Gate

Quad 2-Input AND Gate Features • Outputs Source/Sink 24 mA

Quad 2-Input AND Gate

Quad 2-Input AND Gate Features • Outputs Source/Sink 24 mA

Quad 2-Input AND Gate

Quad 2-Input AND Gate Features • Outputs Source/Sink 24 mA

Quad 2-Input AND Gate

Quad 2-Input AND Gate Features • Outputs Source/Sink 24 mA

Quad 2-Input AND Gate

Quad 2-Input AND Gate Features • Outputs Source/Sink 24 mA

Dual JK Flip-Flop (with Separate Clear and Clock)

Description The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors which connect the master and slave sections. Feature

Dual JK Flip-Flop (with Separate Clear and Clock)

Description The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors which connect the master and slave sections. Feature

Dual JK Flip-Flop (with Separate Clear and Clock)

Description The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors which connect the master and slave sections. Feature

Dual JK Flip-Flop (with Separate Clear and Clock)

Description The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors which connect the master and slave sections. Feature

Dual JK Negative Edge-Triggered Flip-Flop

Description The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flip-flop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will p

Dual JK Negative Edge-Triggered Flip-Flop

Description The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flipflop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will

Dual JK Negative Edge-Triggered Flip-Flop

Description The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flipflop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will

Dual JK Negative Edge-Triggered Flip-Flop

Description The HD74AC112/HD74ACT112 features individual J, K, Clock and asynchronous Set and Clear inputs to each flipflop. When the clock goes High, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may change when the clock is High and the bistable will

Dual Retriggerable Resettable Multivibrator

Description Each half of the HD74AC123A features retriggerable capability, complementary dc level triggering and overriding Direct Clear. When a circuit is in the quasi-stable (delay) state, another trigger applied to the inputs (per the Truth Table) will cause the delay period to start again, wi

Dual Retriggerable Resettable Multivibrator

Description Each half of the HD74AC123A features retriggerable capability, complementary dc level triggering and overriding Direct Clear. When a circuit is in the quasi-stable (delay) state, another trigger applied to the inputs (per the Truth Table) will cause the delay period to start again,

Dual Retriggerable Resettable Multivibrator

Description Each half of the HD74AC123A features retriggerable capability, complementary dc level triggering and overriding Direct Clear. When a circuit is in the quasi-stable (delay) state, another trigger applied to the inputs (per the Truth Table) will cause the delay period to start again,

Dual Retriggerable Resettable Multivibrator

Description Each half of the HD74AC123A features retriggerable capability, complementary dc level triggering and overriding Direct Clear. When a circuit is in the quasi-stable (delay) state, another trigger applied to the inputs (per the Truth Table) will cause the delay period to start again,

Dual Retriggerable Resettable Multivibrator

Description Each half of the HD74AC123A features retriggerable capability, complementary dc level triggering and overriding Direct Clear. When a circuit is in the quasi-stable (delay) state, another trigger applied to the inputs (per the Truth Table) will cause the delay period to start again,

Quad Buffer/Line Driver with 3-State Output

Description The HD74AC125/HD74ACT125 is an quad buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter/receiver which provides improved PC board density. Features • 3-State Outputs Drive Bus Lines or Buffer Memory Addres

Quad Buffer/Line Driver with 3-State Output

Description The HD74AC125/HD74ACT125 is an quad buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter/receiver which provides improved PC board density. Features • 3-State Outputs Drive Bus Lines orBuffer Memory Address

Quad Buffer/Line Driver with 3-State Output

Description The HD74AC125/HD74ACT125 is an quad buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter/receiver which provides improved PC board density. Features • 3-State Outputs Drive Bus Lines orBuffer Memory Address

Quad Buffer/Line Driver with 3-State Output

Description The HD74AC125/HD74ACT125 is an quad buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter/receiver which provides improved PC board density. Features • 3-State Outputs Drive Bus Lines orBuffer Memory Address

Quad Buffer/Line Driver with 3-State Output

Description The HD74AC125/HD74ACT125 is an quad buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter/receiver which provides improved PC board density. Features • 3-State Outputs Drive Bus Lines orBuffer Memory Address

Quad Buffer/Line Driver with 3-State Output

Description The HD74AC125/HD74ACT125 is an quad buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter/receiver which provides improved PC board density. Features • 3-State Outputs Drive Bus Lines orBuffer Memory Address

Quad Buffer/Line Driver with 3-State Output

Description The HD74AC126/HD74ACT126 is an quad buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter/receiver which provides improved PC board density. Features • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers

Quad Buffer/Line Driver with 3-State Output

Description The HD74AC126/HD74ACT126 is an quad buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter/receiver which provides improved PC board density. Features • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers

Quad Buffer/Line Driver with 3-State Output

Description The HD74AC126/HD74ACT126 is an quad buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter/receiver which provides improved PC board density. Features • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers

Quad Buffer/Line Driver with 3-State Output

Description The HD74AC126/HD74ACT126 is an quad buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter/receiver which provides improved PC board density. Features • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers

1-of-8 Decoder/Demultiplexer

Description The HD74AC138/HD74ACT138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three HD74AC138/HD74ACT138 devices or

1-of-8 Decoder/Demultiplexer

Description The HD74AC138/HD74ACT138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for highspeed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three HD74AC138/HD74ACT138 devices or a

1-of-8 Decoder/Demultiplexer

Description The HD74AC138/HD74ACT138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for highspeed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three HD74AC138/HD74ACT138 devices or a

1-of-8 Decoder/Demultiplexer

Description The HD74AC138/HD74ACT138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for highspeed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three HD74AC138/HD74ACT138 devices or a

1-of-8 Decoder/Demultiplexer

Description The HD74AC138/HD74ACT138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for highspeed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three HD74AC138/HD74ACT138 devices or a

1-of-8 Decoder/Demultiplexer

Description The HD74AC138/HD74ACT138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally suited for highspeed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder using just three HD74AC138/HD74ACT138 devices or a

Dual 1-of-4 Decoder/Demultiplexer

Description The HD74AC139/HD74ACT139 is a high-speed, dual 1-of-4 decoder/demultiplexer. The device has two independent decoders, each accepting two inputs and providing four mutually-exclusive active-Low outputs. Each decoder has an active-Low Enable input which can be used as a data input for

Dual 1-of-4 Decoder/Demultiplexer

Description The HD74AC139/HD74ACT139 is a high-speed, dual 1-of-4 decoder/demultiplexer. The device has two independent decoders, each accepting two inputs and providing four mutually-exclusive active-Low outputs. Each decoder has an active-Low Enable input which can be used as a data input for

Dual 1-of-4 Decoder/Demultiplexer

Description The HD74AC139/HD74ACT139 is a high-speed, dual 1-of-4 decoder/demultiplexer. The device has two independent decoders, each accepting two inputs and providing four mutually-exclusive active-Low outputs. Each decoder has an active-Low Enable input which can be used as a data input for

Dual 1-of-4 Decoder/Demultiplexer

Description The HD74AC139/HD74ACT139 is a high-speed, dual 1-of-4 decoder/demultiplexer. The device has two independent decoders, each accepting two inputs and providing four mutually-exclusive active-Low outputs. Each decoder has an active-Low Enable input which can be used as a data input for

Dual 1-of-4 Decoder/Demultiplexer

Description The HD74AC139/HD74ACT139 is a high-speed, dual 1-of-4 decoder/demultiplexer. The device has two independent decoders, each accepting two inputs and providing four mutually-exclusive active-Low outputs. Each decoder has an active-Low Enable input which can be used as a data input for