Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications

General Description The HC2509C is a low-skew, low jitter, phase-locked loop(PLL) clock driver, distributing high frequency clock signals for SDRAM. Features ● Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications ● Supports PC-100 and Meets “PC100 SDRAM registered DIMM Specif

Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications

General Description The HC2510C is a low-skew, low jitter, phase-locked loop(PLL) clock driver, distributing high frequency clock signals for SDRAM Features ● Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications ● Supports PC-100 and Meets “PC100 SDRAM registered DIMM Specifi

Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications

General Description The HC2510C is a low-skew, low jitter, phase-locked loop(PLL) clock driver, distributing high frequency clock signals for SDRAM Features ● Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications ● Supports PC-100 and Meets “PC100 SDRAM registered DIMM Specifi

Dual 4-Input Data Selector/Multiplexer with 3-State Otputs

The SL74HC253 is identical in pinout to the LS/ALS253. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The Address Inputs select one of four Data Inputs from each multiplexer. Each multiplexer has an active-low Output

QUAD 2 CHANNEL MULTIPLEXER 3-STATE

DESCRIPTION The 74VHC257 is an advanced high-speed CMOS QUAD 2-CHANNEL MULTIPLEXER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. ■ HIGH SPEED: tPD = 3.7ns (TYP.) at VCC = 5V ■ LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA=25°C ■ HIGH NOISE I

QUAD 2-CHANEL MULTIPLEXER (3-STATE)

Quad 2-Input Data Selector/Multiplexer with 3-State Outputs

The SL74HC257 is identical in pinout to the LS/ALS257. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device selects a (4-bit) nibble from either the A or B inputs as determined by the Select input. The nibble i

Quad. 2-to-1-line Data Selectors/Multiplexers(with noninverted 3-state outputs)

Description The large output drive capability coupled with the 3-state feature make this device ideal for interfacing with bus lines in a bus organized system. When the output control input line is taken high, the outputs of all four multiplexers are sent into a high impedance state. When the out

Hybrid Coupler 3 dB, 90o

文件：1.64997 Mbytes Page：9 Pages

SMD 3dB90°混合电桥

SMD 3dB90°混合电桥

Hybrid Coupler 3 dB, 90o

文件：1.54908 Mbytes Page：9 Pages

Hybrid Coupler 3 dB, 90o

文件：1.45699 Mbytes Page：9 Pages

SMD 3dB90°混合电桥

Hybrid Coupler 3 dB, 90o

文件：1.44816 Mbytes Page：9 Pages

90 Degree Hybrid 2.30 GHz-2.65 GHz

文件：746.48 Kbytes Page：4 Pages

90 Degree Hybrid 2.30 GHz-2.65 GHz

文件：401.52 Kbytes Page：5 Pages

Quartz SMD, Ceramic

文件：174.11 Kbytes Page：1 Pages

Quartz SMD, Ceramic

文件：174.11 Kbytes Page：1 Pages

Quartz SMD, Ceramic

文件：174.11 Kbytes Page：1 Pages

包装：散装 描述：TAPE,LONG LEADER 3/8\ 工具 专用工具

包装：散装 描述：TAPE,LONG LEADER 3/8\ 工具 专用工具

High Speed CMOS Logic Quad 2-Input Multiplexer with Three-State Non-Inverting Outputs

文件：52.16 Kbytes Page：7 Pages

Hybrid Coupler 3 dB, 90o

文件：2.14767 Mbytes Page：9 Pages