Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications

General Description The HC2509C is a low-skew, low jitter, phase-locked loop(PLL) clock driver, distributing high frequency clock signals for SDRAM. Features ● Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications ● Supports PC-100 and Meets “PC100 SDRAM registered DIMM Specif

Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications

50-150 MHz 1:9 SDRAM clock driver

DESCRIPTION The PCK2509S is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLLto precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The PC

50-150 MHz 1:9 SDRAM clock driver

DESCRIPTION The PCK2509SA is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The

50-150 MHz 1:9 SDRAM clock driver

DESCRIPTION The PCK2509S is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLLto precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The PC

VIDEO SUPER INPOSER WITH Y-C MIXER

文件：194 Kbytes Page：5 Pages

VIDEO SUPER INPOSER WITH Y-C MIXER

文件：194 Kbytes Page：5 Pages