CDx4HC(T)259 High-Speed SMOS Logic 8-Bit Addressable Latch

1 Features • Buffered inputs and outputs • Four operating modes • Typical propagation delay of 15ns at VCC = 5V, CL = 15pF, TA = 25oC • Fanout (over temperature range) – Standard Outputs: 10 LSTTL loads – Bus driver outputs: 15 LSTTL loads • Wide operating temperature range: -55oC to 125oC

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC ADDRESSABLE LATCH 16-SOIC 集成电路（IC） 锁存器

High-Speed CMOS Logic 8-Bit Addressable Latch

文件：271.45 Kbytes Page：12 Pages

High-Speed CMOS Logic 8-Bit Addressable Latch

文件：278.39 Kbytes Page：14 Pages

High-Speed CMOS Logic 8-Bit Addressable Latch

文件：428 Kbytes Page：16 Pages

High-Speed CMOS Logic 8-Bit Addressable Latch

文件：457.82 Kbytes Page：16 Pages

High-Speed CMOS Logic 8-Bit Addressable Latch

文件：428 Kbytes Page：16 Pages

High-Speed CMOS Logic 8-Bit Addressable Latch

文件：278.39 Kbytes Page：14 Pages

High-Speed CMOS Logic 8-Bit Addressable Latch

文件：457.82 Kbytes Page：16 Pages

High-Speed CMOS Logic 8-Bit Addressable Latch

文件：428 Kbytes Page：16 Pages

High-Speed CMOS Logic 8-Bit Addressable Latch

文件：457.82 Kbytes Page：16 Pages

8-bit addressable latch

GENERAL DESCRIPTION The 74HC/HCT259 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Combines demultiplexer and 8-bit latch • Serial-to-parallel capability • Outp

8-bit addressable latch

8-bit addressable latch

1. General description The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed l

8-bit addressable latch

8-bit addressable latch

1. General description The 74HC259; 74HCT259 is an 8-bit addressable latch. The device features four modes of operation. In the addressable latch mode, data on the D input is written into the latch addressed by the inputs A0 to A3. The addressed latch will follow the data input, non-addressed l