24位FPD-LINK II接收器

GM8906C型24位FPD-LINK II接收器主要用于视频/图像传输中的接收部分，其主要功能是实现将1路高速CML差分信号转换为并行的24bit的RGB数据以及3位控制信号（HS/VS/DE）输出。\n 芯片内部集成终端电阻，可通过外部I/0或I2C总线进行配置，支持power down模式。芯片core电源VDDn为1.8V，I/O电源VDDIO可支持3.3V和1.8V两种电压。输入时钟频率为5MHz~60MHz，总数据率最高可达1.44Gbps。\n 本器件在60MHz以下时钟频段，可以与DS90UR906Q兼容，通过配置可功能兼容DS90UR241、DS99R241和DS • 输入信号：CML信号；\n• 输出信号：LVTTL/LVCMOS信号；\n• 参考时钟频率：5MHz～60MHz；\n• 输出时钟采样模式为上升/下降沿可选；\n• 最大数据率1.44Gbps；\n• 28：1的数据压缩；\n• 全集成锁相环，无需外部元件；\n• 应用方式：交流耦合；\n• 封装形式：QFN60；\n• 工作温度范围：－40℃~85℃；;

BIDIRECTIONAL 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER WITH BACK-EMF SENSING

The A8906CLB is a bidirectional three-phase brushless dc motor controller/driver. The three half-bridge outputs are low on-resistance nchannel DMOS devices capable of driving up to 1 A. The A8906CLB provides complete, reliable, self-contained back-EMF sensing motor startup and running algorithms.

BIDIRECTIONAL 3-PHASE BRUSHLESS DC MOTOR CONTROLLER/DRIVER WITH BACK-EMF SENSING

The A8906CLB is a bidirectional three-phase brushless dc motor controller/driver. The three half-bridge outputs are low on-resistance nchannel DMOS devices capable of driving up to 1 A. The A8906CLB provides complete, reliable, self-contained back-EMF sensing motor startup and running algorithms.

AM/FM Digital Phase-Locked Loop Synthesizer

文件：169.58 Kbytes Page：8 Pages

AM/FM Digital Phase-Locked Loop Synthesizer

文件：169.58 Kbytes Page：8 Pages

500MHZ 4 MODULUS DIVIDER

文件：126.55 Kbytes Page：3 Pages