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GAL16V8D价格
参考价格：￥16.8516
型号：GAL16V8D-15LJN 品牌：Lattice Semiconductor 备注：这里有GAL16V8D多少钱，2025年最近7天走势，今日出价，今日竞价，GAL16V8D批发/采购报价，GAL16V8D行情走势销售排行榜，GAL16V8D报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
GAL16V8D | High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 |   | |
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | |
GAL16V8D产品属性
- 类型
描述
- 型号
GAL16V8D
- 制造商
LATTICE
- 制造商全称
Lattice Semiconductor
- 功能描述
High Performance E2CMOS PLD Generic Array Logic
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
LITTICE |
25+ |
PLCC |
3200 |
全新原装、诚信经营、公司现货销售 |
|||
LATTICE/莱迪斯 |
QQ咨询 |
DIP20 |
825 |
全新原装 研究所指定供货商 |
|||
LITTICE |
23+ |
PLCC |
7512 |
绝对全新原装!现货!特价!请放心订购! |
|||
Lattice(莱迪斯) |
24+ |
20-DIP(0.300 |
5538 |
||||
GAL |
22+ |
DIP |
30000 |
十七年VIP会员,诚信经营，一手货源，原装正品可零售！ |
|||
LATTICE/莱迪斯 |
25+ |
PLCC |
30000 |
全新原装,假一赔十,价格优势 |
|||
LATTICE |
2021+ |
DIP |
16800 |
全新原装正品,自家优势现货 |
|||
LATTICE |
2015+ |
PLCC |
19889 |
一级代理原装现货,特价热卖! |
|||
Lattice(莱迪思) |
1236+ |
PDIP-20 |
12300 |
可编程逻辑 IC ,SPLD - 简单可编程逻辑器件 全新原装进口正品现货 |
|||
LATTICE |
原厂封装 |
9800 |
原装进口公司现货假一赔百 |
GAL16V8D芯片相关品牌
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開發板及套件 - ARM This new Dev Board version has the same build as the existing 1 GB Dev Board with 4 GB RAM built in.
2021-1-18GAL16V8D-15LJN
搜索： SMD/SMT SPLD - 简单可编程逻辑器件 , TSSOP-20 SPLD - 简单可编程逻辑器件 , TSSOP-20 SPLD - 简单可编程逻辑器件 , STQFN-12 SPLD - 简单可编程逻辑器件
2020-7-13GAL16V8D-15LD/883产品规格参数
GAL16V8D-15LD/883
2020-7-10GAL16V8D-15LD/883
SPLD - 简单可编程逻辑器件
2019-12-18
DdatasheetPDF页码索引
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