型号 功能描述 生产厂家 企业 LOGO 操作

High Performance E2CMOS PLD Generic Array Logic

Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

All Devices Discontinued

Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on

Lattice

莱迪思

High Performance E2CMOS PLD

文件:340.72 Kbytes Page:23 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:395.51 Kbytes Page:22 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:654.14 Kbytes Page:24 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:339.82 Kbytes Page:23 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:654.14 Kbytes Page:24 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:339.82 Kbytes Page:23 Pages

Lattice

莱迪思

High Performance E2CMOS PLD

文件:340.72 Kbytes Page:23 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:395.51 Kbytes Page:22 Pages

Lattice

莱迪思

封装/外壳:20-LCC(J 形引线) 包装:管件 描述:IC CPLD 8MC 25NS 20PLCC 集成电路(IC) CPLD(复杂可编程逻辑器件)

ETC

知名厂家

封装/外壳:20-LCC(J 形引线) 包装:管件 描述:IC CPLD 8MC 25NS 20PLCC 集成电路(IC) CPLD(复杂可编程逻辑器件)

ETC

知名厂家

High Performance E2CMOS PLD

文件:340.72 Kbytes Page:23 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:654.14 Kbytes Page:24 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:654.14 Kbytes Page:24 Pages

Lattice

莱迪思

IC CPLD 8MC 25NS 20PLCC

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:339.82 Kbytes Page:23 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:654.14 Kbytes Page:24 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:395.51 Kbytes Page:22 Pages

Lattice

莱迪思

High Performance E2CMOS PLD

文件:340.72 Kbytes Page:23 Pages

Lattice

莱迪思

IC CPLD 8MC 25NS 20DIP

Lattice

莱迪思

IC CPLD 8MC 25NS 20DIP

Lattice

莱迪思

High Performance E2CMOS PLD

文件:340.72 Kbytes Page:23 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:339.82 Kbytes Page:23 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:654.14 Kbytes Page:24 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:395.51 Kbytes Page:22 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:654.14 Kbytes Page:24 Pages

Lattice

莱迪思

High Performance E2CMOS PLD

文件:340.72 Kbytes Page:23 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:654.14 Kbytes Page:24 Pages

Lattice

莱迪思

High Performance E2CMOS PLD

文件:340.72 Kbytes Page:23 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:339.82 Kbytes Page:23 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:654.14 Kbytes Page:24 Pages

Lattice

莱迪思

High Performance E2CMOS PLD

文件:340.72 Kbytes Page:23 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:654.14 Kbytes Page:24 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:339.82 Kbytes Page:23 Pages

Lattice

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:395.51 Kbytes Page:22 Pages

Lattice

莱迪思

GAL16V8D-25产品属性

  • 类型

    描述

  • 型号

    GAL16V8D-25

  • 功能描述

    SPLD - 简单可编程逻辑器件 5V 16 I/O

  • RoHS

  • 制造商

    Texas Instruments

  • 逻辑系列

    TICPAL22V10Z

  • 大电池数量

    10

  • 最大工作频率

    66 MHz

  • 延迟时间

    25 ns

  • 工作电源电压

    4.75 V to 5.25 V

  • 电源电流

    100 uA

  • 最大工作温度

    + 75 C

  • 最小工作温度

    0 C

  • 安装风格

    Through Hole

  • 封装/箱体

    DIP-24

更新时间:2025-12-23 13:28:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
LATTICE原现
24+
DIP-20
9600
原装现货,优势供应,支持实单!
LATTICE/莱迪斯
24+
DIP20
33487
郑重承诺只做原装进口现货
2023+
5800
进口原装,现货热卖
2023+
10000
进口原装现货
LATTICE/莱迪斯
21+
DIP20
1709
LATTICE
24+
NA
3600
只做原装正品现货 欢迎来电查询15919825718
Lattice Semiconductor Corporat
23+
20-DIP
11200
主营:汽车电子,停产物料,军工IC
LATTICE/莱迪斯
23+
20-PDIP
98900
原厂原装正品现货!!
Lattice
23+
DIP
8560
受权代理!全新原装现货特价热卖!
LATTICE/莱迪斯
25+
DIP20
2677
全新原装正品支持含税

GAL16V8D-25数据表相关新闻