位置：首页 > IC中文资料第705页 > GAL16V8D-25
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 |   | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic Description The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times ( Features •HIGH PERFORMANCE | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
All Devices Discontinued Features •HIGH PERFORMANCE E2CMOS®TECHNOLOGY —3.5 ns Maximum Propagation Delay —Fmax = 250 MHz —3.0 ns Maximum from Clock Input to Data Output —UltraMOS® Advanced CMOS Technology •50 to 75 REDUCTION IN POWER FROM BIPOLAR —75mA Typ Icc on Low Power Device —45mA Typ Icc on | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：395.51 Kbytes Page：22 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：339.82 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：339.82 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：395.51 Kbytes Page：22 Pages | Lattice 莱迪思 | | ||
封装/外壳：20-LCC（J 形引线） 包装：管件 描述：IC CPLD 8MC 25NS 20PLCC 集成电路（IC） CPLD（复杂可编程逻辑器件） | ETC 知名厂家 | ETC | | |
封装/外壳：20-LCC（J 形引线） 包装：管件 描述：IC CPLD 8MC 25NS 20PLCC 集成电路（IC） CPLD（复杂可编程逻辑器件） | ETC 知名厂家 | ETC | | |
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
IC CPLD 8MC 25NS 20PLCC | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：339.82 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：395.51 Kbytes Page：22 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
IC CPLD 8MC 25NS 20DIP | Lattice 莱迪思 | | ||
IC CPLD 8MC 25NS 20DIP | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：339.82 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：395.51 Kbytes Page：22 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：339.82 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD 文件：340.72 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：654.14 Kbytes Page：24 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：339.82 Kbytes Page：23 Pages | Lattice 莱迪思 | | ||
High Performance E2CMOS PLD Generic Array Logic? 文件：395.51 Kbytes Page：22 Pages | Lattice 莱迪思 | |
GAL16V8D-25产品属性
- 类型
描述
- 型号
GAL16V8D-25
- 功能描述
SPLD - 简单可编程逻辑器件 5V 16 I/O
- RoHS
否
- 制造商
Texas Instruments
- 逻辑系列
TICPAL22V10Z
- 大电池数量
10
- 最大工作频率
66 MHz
- 延迟时间
25 ns
- 工作电源电压
4.75 V to 5.25 V
- 电源电流
100 uA
- 最大工作温度
+ 75 C
- 最小工作温度
0 C
- 安装风格
Through Hole
- 封装/箱体
DIP-24
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
LATTICE |
20+ |
DIP20 |
35830 |
原装优势主营型号-可开原型号增税票 |
|||
LATTE/莱迪斯 |
24+ |
NA/ |
31 |
优势代理渠道,原装正品,可全系列订货开增值税票 |
|||
LATTICE/莱迪斯 |
25+ |
20-PDIP |
996880 |
只做原装,欢迎来电资询 |
|||
10+ |
DIP |
8 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
||||
LATTICE/莱迪斯 |
21+ |
DIP20 |
1709 |
||||
LATTICE |
2430+ |
DIP20 |
8540 |
只做原装正品假一赔十为客户做到零风险!! |
|||
LATTICE/莱迪斯 |
23+ |
20-PDIP |
98900 |
原厂原装正品现货!! |
|||
2023+ |
10000 |
进口原装现货 |
|||||
LATTICE |
24+ |
NA |
16087 |
只做原装正品现货 欢迎来电查询15919825718 |
|||
LATTICE/莱迪斯 |
25+ |
DIP20 |
880000 |
明嘉莱只做原装正品现货 |
GAL16V8D-25规格书下载地址
GAL16V8D-25参数引脚图相关
- ic交易
- ic厂家
- ic查询
- IC插座
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- ic采购
- IC(集成电路)
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- HDD
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- gps模块
- gpib
- GL850G
- gfd
- GALI-39
- GALI-33
- GALI-3
- GALI-29
- GALI-24
- GALI-21
- GALI-2
- GALI-19
- GALI-1
- GALI_59
- GALI_49
- GALI_39
- GALI_29
- GALI_19
- GAL6002
- GAL6001
- GAL504P
- GAL504N
- GAL20V8
- GAL1883
- GAL16V8D-25QP
- GAL16V8D-25QJSB338
- GAL16V8D-25QJNI
- GAL16V8D-25QJN
- GAL16V8D-25QJI
- GAL16V8D25QJI
- GAL16V8D-25QJ
- GAL16V8D-25LS
- GAL16V8D-25LPNI
- GAL16V8D-25LPN
- GAL16V8D25LPN
- GAL16V8D-25LPI
- GAL16V8D-25LP
- GAL16V8D25LP
- GAL16V8D-25LJNI
- GAL16V8D-25LJN
- GAL16V8D25LJN
- GAL16V8D-25LJI
- GAL16V8D-25LJ
- GAL16V8D25LJ
- GAL16V8D-20QPNI
- GAL16V8D-20QPI
- GAL16V8D-20QJNI
- GAL16V8D-20QJI
- GAL16V8D-15QPN
- GAL16V8D-15QP
- GAL16V8D-15QJN
- GAL16V8D-15QJ
- GAL16V8D-15LS
- GAL16V8D-15LPNI
- GAL16V8D-15LPN
- GAL16V8D15LPN
- GAL16V8D-15LPI
- GAL16V8D-15LP
- GAL16V8D15LP
- GAL16V8D-15LJNI
- GAL16V8D-15LJN
- GAL16V8D-15LJI
- GAL16V8D-15LJ
- GAL16V8D15LJ
- GAL16V8
- GAH504P
- GAH504N
- GAH404
- GAH403
- GAH402
- GAH401
- GAH304
- GAH303
- GAH302
- GAH301
- GAG01Z
- GAG01Y
- GAG01A
- GAG01
- GABJ506
- GABJ504
- GABJ503
- GABJ502
- GABJ501
GAL16V8D-25数据表相关新闻
GAL16V8D-25LPN
GAL16V8D-25LPN,全新.当天发货0755-82732291当天发货或门市自取. QQ：1755232575 /QQ：1157611585，微信号:87680558.
2021-4-13GAL16V8D-15LJN
搜索： SMD/SMT SPLD - 简单可编程逻辑器件 , TSSOP-20 SPLD - 简单可编程逻辑器件 , TSSOP-20 SPLD - 简单可编程逻辑器件 , STQFN-12 SPLD - 简单可编程逻辑器件
2020-7-13GAL16V8D-20LD/883产品技术参数
GAL16V8D-20LD/883产品技术参数
2020-7-10GAL16V8D-25LPNI
GAL16V8D-25LPNI
2019-12-20GAL16V8D-15LPN，集成电路（IC）
全新原装，公司现货销售
2019-8-21GAL16V8D-25LPN公司原装现货/随时可以发货
瀚佳科技(深圳)有限公司 专业为工厂一站式BOM配单服务
2019-4-16
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