型号 功能描述 生产厂家 企业 LOGO 操作
DM74LS73A

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra

Fairchild

仙童半导体

DM74LS73A

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

文件:121.86 Kbytes Page:6 Pages

NSC

国半

DM74LS73A

DUAL NEGATIVE-EDGE-TRIGGERED MASTER-SLAVE J-K FLIP-FLOPS WITH CLEAR AND COMPLEMENTARY OUTPUTS

TI

德州仪器

DM74LS73A

DUAL NEGATIVE-EDGE-TRIGGERED MASTER-SLAVE J-K FLIP-FLOPS WITH CLEAR AND COMPLEMENTARY OUTPUTS

文件:91.15 Kbytes Page:3 Pages

NSC

国半

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra

Fairchild

仙童半导体

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra

Fairchild

仙童半导体

DUAL NEGATIVE-EDGE-TRIGGERED MASTER-SLAVE J-K FLIP-FLOPS WITH CLEAR AND COMPLEMENTARY OUTPUTS

文件:91.15 Kbytes Page:3 Pages

NSC

国半

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

文件:121.86 Kbytes Page:6 Pages

NSC

国半

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

文件:121.86 Kbytes Page:6 Pages

NSC

国半

封装/外壳:14-DIP(0.300",7.62mm) 功能:主复位 包装:管件 描述:IC FF JK TYPE DUAL 1BIT 14DIP 集成电路(IC) 触发器

ONSEMI

安森美半导体

DUAL NEGATIVE-EDGE-TRIGGERED MASTER-SLAVE J-K FLIP-FLOPS WITH CLEAR AND COMPLEMENTARY OUTPUTS

文件:91.15 Kbytes Page:3 Pages

NSC

国半

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

文件:121.86 Kbytes Page:6 Pages

NSC

国半

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP TheSN54LS/74LS73A offers individual J, K, clear, and clock inputs.These dualflip-flops aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the

Motorola

摩托罗拉

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra

Fairchild

仙童半导体

Dual J-K Flip-Flops(with Clear)

Dual J-K Flip-Flops(with Clear)

HitachiHitachi Semiconductor

日立日立公司

DUAL J-K FLIP-FLOPS WITH CLEAR

文件:206.08 Kbytes Page:13 Pages

TI

德州仪器

DUAL J-K FLIP-FLOPS WITH CLEAR

文件:206.08 Kbytes Page:13 Pages

TI

德州仪器

DM74LS73A产品属性

  • 类型

    描述

  • 型号

    DM74LS73A

  • 制造商

    Fairchild Semiconductor Corporation

更新时间:2025-12-25 10:32:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
M
22+
PDIP
20000
公司只有原装 品质保证
M
QQ咨询
PDIP
312
全新原装 研究所指定供货商
NAT
05+
原厂原装
4471
只做全新原装真实现货供应
NS
23+
SMD
8560
受权代理!全新原装现货特价热卖!
FSC
SOP3.9
1350
正品原装--自家现货-实单可谈
NS
2025+
SOP14
3565
全新原厂原装产品、公司现货销售
NS
22+
DIP-14
8000
原装正品支持实单
ON Semiconductor
24+
14-DIP(0.300
56300
NSC
23+
原装原封
8888
专做原装正品,假一罚百!
FAIRCHILD/仙童
2022+
45
全新原装 货期两周

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