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DM74LS73AN

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the tra

FAIRCHILD

仙童半导体

DM74LS73AN

DUAL NEGATIVE-EDGE-TRIGGERED MASTER-SLAVE J-K FLIP-FLOPS WITH CLEAR AND COMPLEMENTARY OUTPUTS

文件:91.15 Kbytes Page:3 Pages

NSC

国半

DM74LS73AN

Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs

文件:121.86 Kbytes Page:6 Pages

NSC

国半

DM74LS73AN

封装/外壳:14-DIP(0.300",7.62mm) 功能:主复位 包装:管件 描述:IC FF JK TYPE DUAL 1BIT 14DIP 集成电路(IC) 触发器

ONSEMI

安森美半导体

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP TheSN54LS/74LS73A offers individual J, K, clear, and clock inputs.These dualflip-flops aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the

MOTOROLA

摩托罗拉

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP TheSN54LS/74LS73A offers individual J, K, clear, and clock inputs.These dualflip-flops aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the

MOTOROLA

摩托罗拉

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP TheSN54LS/74LS73A offers individual J, K, clear, and clock inputs.These dualflip-flops aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the

MOTOROLA

摩托罗拉

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP TheSN54LS/74LS73A offers individual J, K, clear, and clock inputs.These dualflip-flops aredesigned so that when the clock goes HIGH, the inputs are enabledand data will be accepted. The logic level of the J and K inputs may beallowed to change when the

MOTOROLA

摩托罗拉

DUAL J-K FLIP-FLOPS WITH CLEAR

文件:206.08 Kbytes Page:13 Pages

TI

德州仪器

DM74LS73AN产品属性

  • 类型

    描述

  • 型号

    DM74LS73AN

  • 功能描述

    触发器 Dual J-K Flip-Flop

  • RoHS

  • 制造商

    Texas Instruments

  • 电路数量

    2

  • 逻辑系列

    SN74

  • 逻辑类型

    D-Type Flip-Flop

  • 极性

    Inverting, Non-Inverting

  • 输入类型

    CMOS

  • 传播延迟时间

    4.4 ns

  • 高电平输出电流

    - 16 mA

  • 低电平输出电流

    16 mA

  • 电源电压-最大

    5.5 V

  • 最大工作温度

    + 85 C

  • 安装风格

    SMD/SMT

  • 封装/箱体

    X2SON-8

  • 封装

    Reel

更新时间:2026-5-20 22:59:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
onsemi
25+
14-MDIP
20948
样件支持,可原厂排单订货!
onsemi
25+
14-MDIP
21000
正规渠道,免费送样。支持账期,BOM一站式配齐
M
92+
PDIP
250
一级代理,专注军工、汽车、医疗、工业、新能源、电力
M
QQ咨询
PDIP
312
全新原装 研究所指定供货商
NSC
25+
23
公司优势库存 热卖中!!
NS
22+
DIP-14
8000
原装正品支持实单
METHODEELECT
23+
65480
ON Semiconductor
24+
14-DIP(0.300
56300
ON Semiconductor
23+
14-DIP0.300,7.62mm
7300
专注配单,只做原装进口现货
M
22+
PDIP
20000
公司只有原装 品质保证

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