Hex/Quad D-Type Flip-Flops with Clear

General Description These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. Both have an asynchronous clear input, and the quad (DM74ALS175) version features complementary outputs from each flip-flop. Information at the D inputs meeting the setup time

封装/外壳：16-DIP（0.300"，7.62mm） 功能：主复位 包装：管件 描述：IC FF D-TYPE SNGL 6BIT 16DIP 集成电路（IC） 触发器

Hex/Quad D-Type Flip-Flops with Clear

General Description These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. Both have an asynchronous clear input, and the quad (DM74ALS175) version features complementary outputs from each flip-flop. Information at the D inputs meeting the setup time

Advanced Low Power Schottky Logic

Features High speed – 2ns (Min) propagation delay Direct drop-in replacement for obsolete components in long term programs.

Advanced Low Power Schottky Logic

Features High speed – 2ns (Min) propagation delay Direct drop-in replacement for obsolete components in long term programs.

Hex D flip-flop

DESCRIPTION The 74ALS174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one set

Hex D flip-flop

DESCRIPTION The 74ALS174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one set

Hex D flip-flop

DESCRIPTION The 74ALS174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one set