Hex D flip-flop

DESCRIPTION The 74ALS174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one set

Advanced Low Power Schottky Logic

Features High speed – 2ns (Min) propagation delay Direct drop-in replacement for obsolete components in long term programs.

Advanced Low Power Schottky Logic

Features High speed – 2ns (Min) propagation delay Direct drop-in replacement for obsolete components in long term programs.

Advanced Low Power Schottky Logic

Features High speed – 2ns (Min) propagation delay Direct drop-in replacement for obsolete components in long term programs.

Hex D flip-flop

DESCRIPTION The 74ALS174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one set

Hex D flip-flop

DESCRIPTION The 74ALS174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one set

HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

文件：527.68 Kbytes Page：17 Pages

HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR

文件：527.68 Kbytes Page：17 Pages