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CY7C1353价格
参考价格：￥23.5564
型号：CY7C1353G-100AXC 品牌：Cynergy 3 备注：这里有CY7C1353多少钱，2025年最近7天走势，今日出价，今日竞价，CY7C1353批发/采购报价，CY7C1353行情走势销售排行榜，CY7C1353报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
CY7C1353 | 256Kx18 Flow-Through SRAM with NoBL Architecture Functional Description The CY7C1353 is a 3.3V 256K by 18 Synchronous-Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353 is equipped with the advanced No Bus Latency (NoBL) logic required to | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 |   | |
CY7C1353 | 256Kx18 Flow-Through SRAM with NoBL Architecture | Infineon 英飞凌 | | |
256Kx18 Flow-Through SRAM with NoBL Architecture Functional Description The CY7C1353 is a 3.3V 256K by 18 Synchronous-Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353 is equipped with the advanced No Bus Latency (NoBL) logic required to | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256Kx18 Flow-Through SRAM with NoBL Architecture Functional Description The CY7C1353 is a 3.3V 256K by 18 Synchronous-Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353 is equipped with the advanced No Bus Latency (NoBL) logic required to | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256Kx18 Flow-Through SRAM with NoBL Architecture Functional Description The CY7C1353 is a 3.3V 256K by 18 Synchronous-Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353 is equipped with the advanced No Bus Latency (NoBL) logic required to | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256Kx18 Flow-Through SRAM with NoBL Architecture Functional Description The CY7C1353B is a 3.3V, 256K by 18 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353B is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256Kx18 Flow-Through SRAM with NoBL Architecture Functional Description The CY7C1353B is a 3.3V, 256K by 18 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353B is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256Kx18 Flow-Through SRAM with NoBL Architecture Functional Description The CY7C1353B is a 3.3V, 256K by 18 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353B is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256Kx18 Flow-Through SRAM with NoBL Architecture Functional Description The CY7C1353B is a 3.3V, 256K by 18 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353B is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256Kx18 Flow-Through SRAM with NoBL Architecture Functional Description The CY7C1353B is a 3.3V, 256K by 18 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353B is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256Kx18 Flow-Through SRAM with NoBL Architecture Functional Description The CY7C1353B is a 3.3V, 256K by 18 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353B is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256Kx18 Flow-Through SRAM with NoBL Architecture Functional Description The CY7C1353B is a 3.3V, 256K by 18 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353B is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
256Kx18 Flow-Through SRAM with NoBL Architecture Functional Description The CY7C1353B is a 3.3V, 256K by 18 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353B is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture Functional Description[1] The CY7C1353F is a 3.3V, 256K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353F is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture Functional Description[1] The CY7C1353F is a 3.3V, 256K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353F is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture Functional Description[1] The CY7C1353F is a 3.3V, 256K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353F is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture Functional Description[1] The CY7C1353F is a 3.3V, 256K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353F is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture Functional Description[1] The CY7C1353F is a 3.3V, 256K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353F is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture Functional Description[1] The CY7C1353F is a 3.3V, 256K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353F is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture Functional Description[1] The CY7C1353F is a 3.3V, 256K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353F is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture Functional Description[1] The CY7C1353F is a 3.3V, 256K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353F is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (256K x 18) Flow-through SRAM with NoBL Architecture Functional Description[1] The CY7C1353F is a 3.3V, 256K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353F is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1353G is a 3.3V, 256K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1353G is a 3.3V, 256K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1353G is a 3.3V, 256K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1353G is a 3.3V, 256K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1353G is a 3.3V, 256K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1353G is a 3.3V, 256K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1353G is a 3.3V, 256K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-through SRAM with NoBL??Architecture 文件：575.66 Kbytes Page：13 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-through SRAM with NoBL??Architecture 文件：575.66 Kbytes Page：13 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256 K 횞 18) Flow-Through SRAM with NoBL??Architecture 文件：535.64 Kbytes Page：18 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256 K x 18) Flow-Through SRAM with NoBL??Architecture 文件：552.41 Kbytes Page：19 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256 K x 18) Flow-Through SRAM with NoBL??Architecture 文件：552.41 Kbytes Page：19 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256 K 횞 18) Flow-Through SRAM with NoBL??Architecture 文件：535.64 Kbytes Page：18 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-through SRAM with NoBL??Architecture 文件：575.66 Kbytes Page：13 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
封装/外壳：100-LQFP 包装：托盘 描述：IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路（IC） 存储器 | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
Synchronous SRAM | Infineon 英飞凌 | | ||
Synchronous SRAM | Infineon 英飞凌 | | ||
封装/外壳：100-LQFP 包装：托盘 描述：IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路（IC） 存储器 | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-through SRAM with NoBL??Architecture 文件：575.66 Kbytes Page：13 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-through SRAM with NoBL??Architecture 文件：575.66 Kbytes Page：13 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (256K x 18) Flow-through SRAM with NoBL??Architecture 文件：575.66 Kbytes Page：13 Pages | CypressCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | |
CY7C1353产品属性
- 类型
描述
- 型号
CY7C1353
- 制造商
CYPRESS
- 功能描述
*
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
CYP |
24+/25+ |
7 |
原装正品现货库存价优 |
||||
Cypress(赛普拉斯) |
23+ |
NA |
20094 |
正纳10年以上分销经验原装进口正品做服务做口碑有支持 |
|||
CYPRESS |
20+ |
QFP |
500 |
样品可出,优势库存欢迎实单 |
|||
CYPRESS/赛普拉斯 |
23+ |
QFP |
98900 |
原厂原装正品现货!! |
|||
CYPRESS |
2016+ |
QFP100 |
5500 |
只做原装,假一罚十,公司可开17%增值税发票! |
|||
CYPRESS/赛普拉斯 |
20+ |
TQFP-100 |
1440 |
||||
CYPRESS |
2023+ |
QFP |
50000 |
原装现货 |
|||
CYPRESS/赛普拉斯 |
20+ |
TQFP-100 |
1 |
进口原装现货假一赔万力挺实单 |
|||
CY |
25+ |
TQFP |
4500 |
百分百原装正品 真实公司现货库存 本公司只做原装 可 |
|||
CYPRESS |
23+ |
BGAQFP |
8659 |
原装公司现货!原装正品价格优势. |
CY7C1353规格书下载地址
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瀚佳科技(深圳)有限公司 专业为工厂一站式BOM配单服务
2019-3-29
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