Functional Description[1]

The CY7C1353F is a 3.3V, 256K x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1353F is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions.

Features

• Can support up to 133-MHz bus operations with zero wait states

— Data is transferred on every clock

• Pin compatible and functionally equivalent to ZBT™ devices

• Internally self-timed output buffer control to eliminate the need to use OE

• Registered inputs for flow-through operation

• Byte Write capability

• 256K x 18 common I/O architecture

• 2.5V / 3.3V I/O power supply

• Fast clock-to-output times

— 6.5 ns (for 133-MHz device)

— 7.5 ns (for 117-MHz device)

— 8.0 ns (for 100-MHz device)

— 11.0 ns (for 66-MHz device)

• Clock Enable (CEN) pin to suspend operation

• Synchronous self-timed writes

• Asynchronous Output Enable

• JEDEC-standard 100 TQFP package

• Burst Capability—linear or interleaved burst order

• Low standby power