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CY7C1351价格
参考价格：￥25.9660
型号：CY7C1351G-100AXC 品牌：Cynergy 3 备注：这里有CY7C1351多少钱，2025年最近7天走势，今日出价，今日竞价，CY7C1351批发/采购报价，CY7C1351行情走势销售排行榜，CY7C1351报价。| 型号 | 功能描述 | 生产厂家&企业 | LOGO | 操作 |
|---|---|---|---|---|
CY7C1351 | 128Kx36 Flow-Through SRAM with NoBL TM Architecture Functional Description The CY7C1351 is a 3.3V, 128K by 36 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351 is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 |   | |
CY7C1351 | 4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | |
128Kx36 Flow-Through SRAM with NoBL TM Architecture Functional Description The CY7C1351 is a 3.3V, 128K by 36 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351 is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
128Kx36 Flow-Through SRAM with NoBL TM Architecture Functional Description The CY7C1351 is a 3.3V, 128K by 36 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351 is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
128Kx36 Flow-Through SRAM with NoBL TM Architecture Functional Description The CY7C1351 is a 3.3V, 128K by 36 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351 is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K 횞 36) Flow-Through SRAM with NoBL??Architecture 文件：550.32 Kbytes Page：20 Pages | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K x 36) Flow-Through SRAM with NoBL??Architecture 文件：567.3 Kbytes Page：21 Pages | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
封装/外壳：100-LQFP 包装：卷带（TR）剪切带（CT） 描述：IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路（IC） 存储器 | ETC 知名厂家 | ETC | | |
4-Mbit (128 K 횞 36) Flow-Through SRAM with NoBL??Architecture 文件：550.32 Kbytes Page：20 Pages | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K x 36) Flow-Through SRAM with NoBL??Architecture 文件：567.3 Kbytes Page：21 Pages | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
封装/外壳：100-LQFP 包装：托盘 描述：IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路（IC） 存储器 | ETC 知名厂家 | ETC | | |
4-Mbit (128 K x 36) Flow-Through SRAM with NoBL??Architecture 文件：567.3 Kbytes Page：21 Pages | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K 횞 36) Flow-Through SRAM with NoBL??Architecture 文件：550.32 Kbytes Page：20 Pages | CypressCypressSemiconductor 赛普拉斯赛普拉斯半导体公司 | |
CY7C1351产品属性
- 类型
描述
- 型号
CY7C1351
- 制造商
Cypress Semiconductor
- 功能描述
Electronic Component
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
CYPRESS(赛普拉斯) |
24+ |
LQFP-100 |
5591 |
百分百原装正品,可原型号开票 |
|||
CYPRESS/赛普拉斯 |
24+ |
TQFP100 |
47186 |
郑重承诺只做原装进口现货 |
|||
CYPRESS/赛普拉斯 |
21+ |
QFP |
750 |
原装现货假一赔十 |
|||
Cypress Semiconductor/赛普拉斯 |
两年内 |
NA |
18000 |
实单价格可谈 |
|||
CY |
20+ |
QFP |
3242 |
英卓尔科技,进口原装现货! |
|||
CYPRESS/赛普拉斯 |
25+ |
NA |
880000 |
明嘉莱只做原装正品现货 |
|||
CYPRESS |
25+ |
QFP |
750 |
原装正品,假一罚十! |
|||
CYPRESS |
24+ |
TQFP100 |
2650 |
原装优势!绝对公司现货 |
|||
CYPRESS/赛普拉斯 |
23+ |
QFP100 |
90000 |
一定原装正品 |
|||
Cypress Semiconductor Corp |
23+ |
100-TQFP14x14 |
7300 |
专注配单,只做原装进口现货 |
CY7C1351规格书下载地址
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瀚佳科技(深圳)有限公司 专业为工厂一站式BOM配单服务
2019-3-29
DdatasheetPDF页码索引
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