CY7C1351价格
参考价格：￥25.9660
型号：CY7C1351G-100AXC 品牌：Cynergy 3 备注：这里有CY7C1351多少钱，2026年最近7天走势，今日出价，今日竞价，CY7C1351批发/采购报价，CY7C1351行情走势销售排行榜，CY7C1351报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
CY7C1351 | 128Kx36 Flow-Through SRAM with NoBL TM Architecture Functional Description The CY7C1351 is a 3.3V, 128K by 36 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351 is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 |   | |
CY7C1351 | 4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | |
CY7C1351 | 4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture | INFINEON 英飞凌 | | |
128Kx36 Flow-Through SRAM with NoBL TM Architecture Functional Description The CY7C1351 is a 3.3V, 128K by 36 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351 is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
128Kx36 Flow-Through SRAM with NoBL TM Architecture Functional Description The CY7C1351 is a 3.3V, 128K by 36 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351 is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
128Kx36 Flow-Through SRAM with NoBL TM Architecture Functional Description The CY7C1351 is a 3.3V, 128K by 36 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351 is equipped with the advanced No Bus Latency™ (NoBL™) logic required | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoBL™ Architecture • Can support up to 133-MHz bus operations with zero wait states\n• Pin compatible and functionally equivalent to ZBT™ devices\n• Registered inputs for flow-through operation\n• 128K x 36 common I/O architecture\n• Fast clock-to-output times\n• Clock Enable (CEN) pin to suspend operation\n• Asynchro; | INFINEON 英飞凌 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mb (128K x 36) Flow-through SRAM with NoB TM Architecture Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through ope | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL??Architecture Functional Description[1] The CY7C1351G is a 3.3V, 128K x 36 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351G is equipped with the advanced No Bus Latency™ (NoBL™) logic requi | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128K x 36) Flow-through SRAM with NoBL™ Architecture | INFINEON 英飞凌 | | ||
4-Mbit (128 K 횞 36) Flow-Through SRAM with NoBL??Architecture 文件：550.32 Kbytes Page：20 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K x 36) Flow-Through SRAM with NoBL??Architecture 文件：567.3 Kbytes Page：21 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
封装/外壳：100-LQFP 包装：卷带（TR）剪切带（CT） 描述：IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路（IC） 存储器 | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K 횞 36) Flow-Through SRAM with NoBL??Architecture 文件：550.32 Kbytes Page：20 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K x 36) Flow-Through SRAM with NoBL??Architecture 文件：567.3 Kbytes Page：21 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
封装/外壳：100-LQFP 包装：托盘 描述：IC SRAM 4.5MBIT PARALLEL 100TQFP 集成电路（IC） 存储器 | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K x 36) Flow-Through SRAM with NoBL??Architecture 文件：567.3 Kbytes Page：21 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | | ||
4-Mbit (128 K 횞 36) Flow-Through SRAM with NoBL??Architecture 文件：550.32 Kbytes Page：20 Pages | CYPRESSCypress Semiconductor 赛普拉斯赛普拉斯半导体公司 | |
CY7C1351产品属性
- 类型
描述
- 存储器格式：
SRAM
- 技术：
SRAM - 同步
- 存储容量：
4.5Mb （128K x 36）
- 时钟频率：
100MHz
- 访问时间：
8ns
- 存储器接口：
并联
- 电压 - 电源：
3.135V ~ 3.6V
- 工作温度：
0°C ~ 70°C（TA）
- 安装类型：
表面贴装
- 封装/外壳：
100-LQFP
- 供应商器件封装：
100-TQFP（14x20）
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
CYPRESS |
26+ |
DIP-16 |
890000 |
一级总代理商原厂原装大批量现货
一站式服务 |
|||
CYPRESS |
25+ |
BGAQFP |
8659 |
原装公司现货!原装正品价格优势. |
|||
CY |
25+23+ |
QFP |
13397 |
绝对原装正品全新进口深圳现货 |
|||
CYPRESS |
22+ |
CDIP-24 |
8000 |
原装正品支持实单 |
|||
Cypress Semiconductor Corp |
24+25+ |
16500 |
全新原厂原装现货!受权代理!可送样可提供技术支持! |
||||
INFINEON |
24+ |
N/A |
10000 |
只做原装,实单最低价支持 |
|||
CY |
20+ |
QFP |
3242 |
英卓尔科技,进口原装现货! |
|||
CYPRESS |
23+ |
DIP-20 |
5000 |
原装正品,假一罚十 |
|||
CYPRESS |
2023+ |
QFP |
53500 |
正品,原装现货 |
|||
CYPRESS |
16+ |
QFP |
2500 |
进口原装现货/价格优势! |
CY7C1351规格书下载地址
CY7C1351参数引脚图相关
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- CY7C1356CV25-166AXC
- CY7C1356C-250AXC
- CY7C1356C-166AXI
- CY7C1356C-166AXC
- CY7C1355C-133AXC
- CY7C1355B-100AC
- CY7C1354CV25-200AXC
- CY7C1354CV25-166BZC
- CY7C1354CV25-166AXC
- CY7C1354C-200AXI
- CY7C1354C-200AXC
- CY7C1354C-166AXI
- CY7C1354C-166AXC
- CY7C1353S-100AXC
- CY7C1353G-100AXC
- CY7C1352S-133AXC
- CY7C1352G-133AXC
- CY7C1351G-133AXC
- CY7C1351G-100AXC
- CY7C135-15JXC
- CY7C1350S-133AXC
- CY7C1350G-200AXI
- CY7C1350G-200AXCT
- CY7C1350G-200AXC
- CY7C1350G-133AXI
- CY7C1350G-133AXC
- CY7C135
- CY7C1347S-133AXC
- CY7C1347G-250AXC
- CY7C1347G-166AXC
- CY7C1347G-133BGXC
- CY7C1347G-133AXC
- CY7C1345S-100AXC
- CY7C1345G-100AXI
- CY7C1345G-100AXC
- CY7C1339S-133AXC
- CY7C1339G-133AXC
- CY7C1338G-100AXC
- CY7C133
- CY7C1328G-133AXI
- CY7C1327G-166AXC
- CY7C1327G-133AXI
- CY7C132
- CY7C131
- CY7C130
- CY7C129
- CY7C109
- CY7C107
- CY7C057
- CY7C038
- CY7C037
- CY7C028
- CY7C027
- CY7C025
- CY7C024
- CY7C019
- CY7C018
- CY7C016
- CY7C009
- CY7C008
CY7C1351数据表相关新闻
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全新原装
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全新原装
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瀚佳科技(深圳)有限公司 专业为工厂一站式BOM配单服务
2019-3-29
DdatasheetPDF页码索引
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